17101   EVT ResVT = N->getValueType(0);  in PerformVECREDUCE_ADDCombine()  local
17106   if (ResVT == MVT::i32 && N0.getOpcode() == ISD::ADD &&  in PerformVECREDUCE_ADDCombine()
17109     SDValue Red0 = DAG.getNode(ISD::VECREDUCE_ADD, dl, ResVT, N0.getOperand(0));  in PerformVECREDUCE_ADDCombine()
17110     SDValue Red1 = DAG.getNode(ISD::VECREDUCE_ADD, dl, ResVT, N0.getOperand(1));  in PerformVECREDUCE_ADDCombine()
17111     return DAG.getNode(ISD::ADD, dl, ResVT, Red0, Red1);  in PerformVECREDUCE_ADDCombine()
17145     if (ResVT != RetTy || N0->getOpcode() != ExtendCode)  in PerformVECREDUCE_ADDCombine()
17154     if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT ||  in PerformVECREDUCE_ADDCombine()
17176     if (ResVT != RetTy)  in PerformVECREDUCE_ADDCombine()
17181             ResVT.getScalarSizeInBits())  in PerformVECREDUCE_ADDCombine()
17206     if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT ||  in PerformVECREDUCE_ADDCombine()
17213             ResVT.getScalarSizeInBits())  in PerformVECREDUCE_ADDCombine()
17265     return DAG.getNode(ARMISD::VMLAVs, dl, ResVT, A, B);  in PerformVECREDUCE_ADDCombine()
17267     return DAG.getNode(ARMISD::VMLAVu, dl, ResVT, A, B);  in PerformVECREDUCE_ADDCombine()
17275     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
17278     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
17283     return DAG.getNode(ARMISD::VMLAVps, dl, ResVT, A, B, Mask);  in PerformVECREDUCE_ADDCombine()
17286     return DAG.getNode(ARMISD::VMLAVpu, dl, ResVT, A, B, Mask);  in PerformVECREDUCE_ADDCombine()
17294     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
17297     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
17301     return DAG.getNode(ARMISD::VADDVs, dl, ResVT, A);  in PerformVECREDUCE_ADDCombine()
17303     return DAG.getNode(ARMISD::VADDVu, dl, ResVT, A);  in PerformVECREDUCE_ADDCombine()
17309     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
17312     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
17316     return DAG.getNode(ARMISD::VADDVps, dl, ResVT, A, Mask);  in PerformVECREDUCE_ADDCombine()
17318     return DAG.getNode(ARMISD::VADDVpu, dl, ResVT, A, Mask);  in PerformVECREDUCE_ADDCombine()
17324     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
17327     return DAG.getNode(ISD::TRUNCATE, dl, ResVT,  in PerformVECREDUCE_ADDCombine()
17345       return DAG.getNode(ISD::VECREDUCE_ADD, dl, ResVT, Ext);  in PerformVECREDUCE_ADDCombine()
21255 bool ARMTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,  in isExtractSubvectorCheap()  argument
21257   if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))  in isExtractSubvectorCheap()
21260   return (Index == 0 || Index == ResVT.getVectorNumElements());  in isExtractSubvectorCheap()