| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyMachineFunctionInfo.cpp | 50 MVT RegisterVT = TLI.getRegisterType(Ctx, VT); in computeLegalValueVTs() local
52 ValueVTs.push_back(RegisterVT); in computeLegalValueVTs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVISelLowering.h | 61 std::optional<MVT> RegisterVT = std::nullopt) const override {
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1164 MVT &RegisterVT, in getVectorTypeBreakdownMVT() argument
1208 RegisterVT = DestVT; in getVectorTypeBreakdownMVT()
1550 MVT RegisterVT; in computeRegisterProperties() local
1553 NumIntermediates, RegisterVT, this); in computeRegisterProperties()
1557 RegisterTypeForVT[i] = RegisterVT; in computeRegisterProperties()
1619 MVT &RegisterVT) const { in getVectorTypeBreakdown()
1633 RegisterVT = RegisterEVT.getSimpleVT(); in getVectorTypeBreakdown()
1664 RegisterVT = getRegisterType(Context, IntermediateVT); in getVectorTypeBreakdown()
1691 RegisterVT = DestVT; in getVectorTypeBreakdown()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLoweringCall.cpp | 110 MVT RegisterVT; in getRegisterTypeForCallingConv() local
112 std::tie(RegisterVT, NumRegisters) = in getRegisterTypeForCallingConv()
114 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE) in getRegisterTypeForCallingConv()
115 return RegisterVT; in getRegisterTypeForCallingConv()
146 MVT RegisterVT; in getNumRegistersForCallingConv() local
148 std::tie(RegisterVT, NumRegisters) = in getNumRegistersForCallingConv()
150 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE) in getNumRegistersForCallingConv()
177 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
184 RegisterVT = MVT::i8; in getVectorTypeBreakdownForCallingConv()
193 RegisterVT = MVT::v32i8; in getVectorTypeBreakdownForCallingConv()
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| H A D | X86ISelLowering.h | 1625 unsigned &NumIntermediates, MVT &RegisterVT) const override;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.h | 457 std::optional<MVT> RegisterVT) const override { in getNumRegisters() argument
459 if (VT == MVT::i128 && RegisterVT && *RegisterVT == MVT::Untyped) in getNumRegisters()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FunctionLoweringInfo.cpp | 393 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT); in CreateRegs() local
397 Register R = CreateReg(RegisterVT, isDivergent); in CreateRegs()
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| H A D | SelectionDAGBuilder.cpp | 353 MVT RegisterVT; in getCopyFromPartsVector() local
360 NumIntermediates, RegisterVT); in getCopyFromPartsVector()
364 NumIntermediates, RegisterVT); in getCopyFromPartsVector()
369 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); in getCopyFromPartsVector()
370 assert(RegisterVT.getSizeInBits() == in getCopyFromPartsVector()
758 MVT RegisterVT; in getCopyToPartsVector() local
764 RegisterVT); in getCopyToPartsVector()
768 NumIntermediates, RegisterVT); in getCopyToPartsVector()
773 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); in getCopyToPartsVector()
862 MVT RegisterVT = in RegsForValue() local
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| H A D | FastISel.cpp | 1012 MVT RegisterVT = TLI.getRegisterType(CLI.RetTy->getContext(), VT); in lowerCallTo() local
1016 MyFlags.VT = RegisterVT; in lowerCallTo()
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| H A D | SelectionDAG.cpp | 2715 MVT RegisterVT; in getReducedAlign() local
2718 NumIntermediates, RegisterVT); in getReducedAlign()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.h | 325 std::optional<MVT> RegisterVT) const override;
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| H A D | NVPTXISelLowering.cpp | 3317 std::optional<MVT> RegisterVT = std::nullopt) const { in getNumRegisters() argument
3318 if (VT == MVT::i128 && RegisterVT == MVT::i128) in getNumRegisters()
3320 return TargetLoweringBase::getNumRegisters(Context, VT, RegisterVT); in getNumRegisters()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.h | 84 std::optional<MVT> RegisterVT = std::nullopt) const override;
96 MVT &RegisterVT) const override;
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| H A D | RISCVISelLowering.cpp | 2399 std::optional<MVT> RegisterVT) const { in getNumRegisters()
2401 if (VT == (Subtarget.is64Bit() ? MVT::i128 : MVT::i64) && RegisterVT && in getNumRegisters()
2402 *RegisterVT == MVT::Untyped) in getNumRegisters()
2405 return TargetLowering::getNumRegisters(Context, VT, RegisterVT); in getNumRegisters()
2422 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
2424 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT); in getVectorTypeBreakdownForCallingConv()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 1201 MVT &RegisterVT) const;
1208 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv() argument
1210 RegisterVT); in getVectorTypeBreakdownForCallingConv()
1775 MVT RegisterVT; in getRegisterType() local
1778 NumIntermediates, RegisterVT); in getRegisterType()
1779 return RegisterVT; in getRegisterType()
1800 std::optional<MVT> RegisterVT = std::nullopt) const {
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 162 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
171 RegisterVT = MVT::v8i8; in getVectorTypeBreakdownForCallingConv()
180 RegisterVT = MVT::v64i8; in getVectorTypeBreakdownForCallingConv()
190 RegisterVT = MVT::v128i8; in getVectorTypeBreakdownForCallingConv()
197 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT); in getVectorTypeBreakdownForCallingConv()
227 auto [RegisterVT, NumRegisters] = in getRegisterTypeForCallingConv()
229 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE) in getRegisterTypeForCallingConv()
230 return RegisterVT; in getRegisterTypeForCallingConv()
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| H A D | HexagonISelLowering.h | 273 MVT &RegisterVT) const override;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 1254 MVT RegisterVT = getRegisterTypeForCallingConv(Ctx, CC, ArgVT); in analyzeFormalArgumentsCompute() local
1262 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
1266 } else if (ArgVT.isVector() && RegisterVT.isVector() && in analyzeFormalArgumentsCompute()
1267 ArgVT.getScalarType() == RegisterVT.getScalarType()) { in analyzeFormalArgumentsCompute()
1268 assert(ArgVT.getVectorNumElements() > RegisterVT.getVectorNumElements()); in analyzeFormalArgumentsCompute()
1272 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
1280 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
1284 if (RegisterVT.isInteger()) { in analyzeFormalArgumentsCompute()
1286 } else if (RegisterVT.isVector()) { in analyzeFormalArgumentsCompute()
1287 assert(!RegisterVT.getScalarType().isFloatingPoint()); in analyzeFormalArgumentsCompute()
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| H A D | SIISelLowering.h | 45 unsigned &NumIntermediates, MVT &RegisterVT) const override;
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| H A D | SIISelLowering.cpp | 1127 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
1137 RegisterVT = MVT::i32; in getVectorTypeBreakdownForCallingConv()
1140 RegisterVT = VT.isInteger() ? MVT::v2i16 : MVT::v2f16; in getVectorTypeBreakdownForCallingConv()
1141 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
1148 RegisterVT = ScalarVT.getSimpleVT(); in getVectorTypeBreakdownForCallingConv()
1149 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
1156 RegisterVT = MVT::i16; in getVectorTypeBreakdownForCallingConv()
1163 RegisterVT = MVT::i32; in getVectorTypeBreakdownForCallingConv()
1170 RegisterVT = MVT::i32; in getVectorTypeBreakdownForCallingConv()
1171 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.h | 310 unsigned &NumIntermediates, MVT &RegisterVT) const override;
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| H A D | MipsISelLowering.cpp | 124 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
127 RegisterVT = IntermediateVT.getSimpleVT(); in getVectorTypeBreakdownForCallingConv()
133 RegisterVT = getRegisterType(Context, IntermediateVT); in getVectorTypeBreakdownForCallingConv()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 537 MVT &RegisterVT) const override;
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| H A D | AArch64ISelLowering.cpp | 30476 MVT RegisterVT; in getRegisterTypeForCallingConv() local
30479 RegisterVT); in getRegisterTypeForCallingConv()
30480 return RegisterVT; in getRegisterTypeForCallingConv()
30499 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
30501 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT); in getVectorTypeBreakdownForCallingConv()
30502 if (!RegisterVT.isFixedLengthVector() || in getVectorTypeBreakdownForCallingConv()
30503 RegisterVT.getFixedSizeInBits() <= 128) in getVectorTypeBreakdownForCallingConv()
30507 assert(IntermediateVT == RegisterVT && "Unexpected VT mismatch!"); in getVectorTypeBreakdownForCallingConv()
30508 assert(RegisterVT.getFixedSizeInBits() % 128 == 0 && "Unexpected size!"); in getVectorTypeBreakdownForCallingConv()
30512 if (RegisterVT.getSizeInBits() * NumRegs != VT.getSizeInBits()) { in getVectorTypeBreakdownForCallingConv()
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