Searched refs:RegSeq (Results 1 – 7 of 7) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/AsmParser/ |
| H A D | CSKYAsmParser.cpp | 190 RegSeqOp RegSeq; member
206 RegSeq = o.RegSeq; in CSKYOperand()
410 return std::pair<unsigned, unsigned>(RegSeq.RegNumFrom, RegSeq.RegNumTo); in getRegSeq()
493 Op->RegSeq.RegNumFrom = RegNoFrom; in createRegSeq()
494 Op->RegSeq.RegNumTo = RegNoTo; in createRegSeq()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 1477 SDValue RegSeq = createQTuple(Regs); in SelectTable() local
1482 Ops.push_back(RegSeq); in SelectTable()
2176 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectStore() local
2178 SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), N->getOperand(0)}; in SelectStore()
2195 SDValue RegSeq = createZTuple(Regs); in SelectPredicatedStore() local
2204 SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), // predicate in SelectPredicatedStore()
2240 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectPostStore() local
2242 SDValue Ops[] = {RegSeq, in SelectPostStore()
2299 SDValue RegSeq = createQTuple(Regs); in SelectLoadLane() local
2305 SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64), in SelectLoadLane()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 5134 auto RegSeq = createQTuple(Regs, MIB); in selectShuffleVector() local
5136 {RegSeq, IndexLoad->getOperand(0)}); in selectShuffleVector()
6862 Register RegSeq = createQTuple(Regs, MIB); in SelectTable() local
6868 Instr = MIB.buildInstr(Opc, {DstReg}, {Reg, RegSeq, IdxReg}); in SelectTable()
6870 Instr = MIB.buildInstr(Opc, {DstReg}, {RegSeq, IdxReg}); in SelectTable()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 2380 SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVST() local
2384 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain }; in SelectVST()
2401 Ops.push_back(RegSeq); in SelectVST()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.td | 90 // E.g. RegSeq<3,2,2,"s">.ret -> [ "s[0:1]", "s[2:3]" ]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrInfo.td | 432 let Name = "RegSeq"#Suffix;
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXIntrinsics.td | 53 class RegSeq<int n, string prefix> {
54 list<string> ret = !if(n, !listconcat(RegSeq<!sub(n, 1), prefix>.ret,
6472 list<string> reg_names = RegSeq<!size(ptx_regs), "r"#frag>.ret;
|