| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 223 MachineInstr &RegSeq,
920 MachineInstr &RegSeq, in getRegSeqInit() argument
923 assert(RegSeq.isRegSequence()); in getRegSeqInit()
927 for (unsigned I = 1, E = RegSeq.getNumExplicitOperands(); I != E; I += 2) { in getRegSeqInit()
928 MachineOperand &SrcOp = RegSeq.getOperand(I); in getRegSeqInit()
929 unsigned SubRegIdx = RegSeq.getOperand(I + 1).getImm(); in getRegSeqInit()
970 SIFoldOperandsImpl::isRegSeqSplat(MachineInstr &RegSeq) const { in isRegSeqSplat()
972 const TargetRegisterClass *SrcRC = getRegSeqInit(RegSeq, Defs); in isRegSeqSplat()
1032 MRI->getRegClass(RegSeq.getOperand(0).getReg()), AMDGPU::sub0_sub1); in isRegSeqSplat()
1812 MachineInstr *RegSeq = MRI->getVRegDef(UseReg); in foldCopyToAGPRRegSequence() local
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| H A D | SIRegisterInfo.td | 49 // E.g. RegSeq<3,2,2,"s">.ret -> [ "s[0:1]", "s[2:3]" ]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/AsmParser/ |
| H A D | CSKYAsmParser.cpp | 190 RegSeqOp RegSeq; member
206 RegSeq = o.RegSeq; in CSKYOperand()
410 return {RegSeq.RegNumFrom, RegSeq.RegNumTo}; in getRegSeq()
493 Op->RegSeq.RegNumFrom = RegNoFrom; in createRegSeq()
494 Op->RegSeq.RegNumTo = RegNoTo; in createRegSeq()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 1480 SDValue RegSeq = createQTuple(Regs); in SelectTable() local
1485 Ops.push_back(RegSeq); in SelectTable()
2276 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectStore() local
2278 SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), N->getOperand(0)}; in SelectStore()
2295 SDValue RegSeq = createZTuple(Regs); in SelectPredicatedStore() local
2304 SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), // predicate in SelectPredicatedStore()
2340 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectPostStore() local
2342 SDValue Ops[] = {RegSeq, in SelectPostStore()
2399 SDValue RegSeq = createQTuple(Regs); in SelectLoadLane() local
2405 SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64), in SelectLoadLane()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 5269 auto RegSeq = createQTuple(Regs, MIB); in selectShuffleVector() local
5271 {RegSeq, IndexLoad->getOperand(0)}); in selectShuffleVector()
7035 Register RegSeq = createQTuple(Regs, MIB); in SelectTable() local
7041 Instr = MIB.buildInstr(Opc, {DstReg}, {Reg, RegSeq, IdxReg}); in SelectTable()
7043 Instr = MIB.buildInstr(Opc, {DstReg}, {RegSeq, IdxReg}); in SelectTable()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 2371 SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVST() local
2375 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain }; in SelectVST()
2392 Ops.push_back(RegSeq); in SelectVST()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrInfo.td | 432 let Name = "RegSeq"#Suffix;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXIntrinsics.td | 56 class RegSeq<int n, string prefix> {
57 list<string> ret = !if(n, !listconcat(RegSeq<!sub(n, 1), prefix>.ret,
4503 list<string> reg_names = RegSeq<!size(ptx_regs), "r"#frag>.ret;
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