Lines Matching refs:RegSeq
1477 SDValue RegSeq = createQTuple(Regs); in SelectTable() local
1482 Ops.push_back(RegSeq); in SelectTable()
2176 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectStore() local
2178 SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), N->getOperand(0)}; in SelectStore()
2195 SDValue RegSeq = createZTuple(Regs); in SelectPredicatedStore() local
2204 SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), // predicate in SelectPredicatedStore()
2240 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectPostStore() local
2242 SDValue Ops[] = {RegSeq, in SelectPostStore()
2299 SDValue RegSeq = createQTuple(Regs); in SelectLoadLane() local
2305 SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64), in SelectLoadLane()
2310 EVT WideVT = RegSeq.getOperand(1)->getValueType(0); in SelectLoadLane()
2337 SDValue RegSeq = createQTuple(Regs); in SelectPostLoadLane() local
2340 RegSeq->getValueType(0), MVT::Other}; in SelectPostLoadLane()
2344 SDValue Ops[] = {RegSeq, in SelectPostLoadLane()
2361 EVT WideVT = RegSeq.getOperand(1)->getValueType(0); in SelectPostLoadLane()
2391 SDValue RegSeq = createQTuple(Regs); in SelectStoreLane() local
2395 SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64), in SelectStoreLane()
2419 SDValue RegSeq = createQTuple(Regs); in SelectPostStoreLane() local
2426 SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64), in SelectPostStoreLane()