223       MachineInstr &RegSeq,
920     MachineInstr &RegSeq,  in getRegSeqInit()  argument
923   assert(RegSeq.isRegSequence());  in getRegSeqInit()
927   for (unsigned I = 1, E = RegSeq.getNumExplicitOperands(); I != E; I += 2) {  in getRegSeqInit()
928     MachineOperand &SrcOp = RegSeq.getOperand(I);  in getRegSeqInit()
929     unsigned SubRegIdx = RegSeq.getOperand(I + 1).getImm();  in getRegSeqInit()
970 SIFoldOperandsImpl::isRegSeqSplat(MachineInstr &RegSeq) const {  in isRegSeqSplat()
972   const TargetRegisterClass *SrcRC = getRegSeqInit(RegSeq, Defs);  in isRegSeqSplat()
1032       MRI->getRegClass(RegSeq.getOperand(0).getReg()), AMDGPU::sub0_sub1);  in isRegSeqSplat()
1812   MachineInstr *RegSeq = MRI->getVRegDef(UseReg);  in foldCopyToAGPRRegSequence()  local
1813   if (!RegSeq || !RegSeq->isRegSequence())  in foldCopyToAGPRRegSequence()
1828   unsigned NumRegSeqOperands = RegSeq->getNumOperands();  in foldCopyToAGPRRegSequence()
1832     MachineOperand &RegOp = RegSeq->getOperand(I);  in foldCopyToAGPRRegSequence()
1833     unsigned SubRegIdx = RegSeq->getOperand(I + 1).getImm();  in foldCopyToAGPRRegSequence()