| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kRegisterInfo.td | 102 let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<8,16,16>]> in
104 let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<16,16,16>]> in
106 let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<32,32,32>]> in
110 let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<16,16,16>]> in
112 let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<32,32,32>]> in
115 let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<32,32,32>]> in
120 let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<16,16,16>]> in
122 let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<32,32,32>]> in
125 let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<32,32,32>]> in
129 let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<32,32,32>]> in
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 91 const MipsRegisterInfo &RegInfo; member in __anonaded3df10111::ExpandPseudo
100 RegInfo(*Subtarget.getRegisterInfo()) {} in ExpandPseudo()
171 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond()
175 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0); in expandLoadCCond()
186 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond()
192 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0); in expandStoreCCond()
204 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC()
208 Register Lo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandLoadACC()
209 Register Hi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandLoadACC()
213 TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0); in expandLoadACC()
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| H A D | MipsSERegisterInfo.cpp | 152 const MipsRegisterInfo *RegInfo = in eliminateFI() local
179 else if (RegInfo->hasStackRealignment(MF)) { in eliminateFI()
220 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); in eliminateFI() local
221 Register Reg = RegInfo.createVirtualRegister(PtrRC); in eliminateFI()
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| H A D | Mips16ISelDAGToDAG.cpp | 63 MachineRegisterInfo &RegInfo = MF.getRegInfo(); in initGlobalBaseReg() local
69 V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
70 V1 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
71 V2 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
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| H A D | MipsSEISelLowering.cpp | 3091 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitBPOSGE32() local
3122 Register VR2 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32()
3128 Register VR1 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32()
3160 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitMSACBranchPseudo() local
3191 Register RD1 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo()
3197 Register RD2 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo()
3227 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitCOPY_FW() local
3238 Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass); in emitCOPY_FW()
3245 Register Wt = RegInfo.createVirtualRegister( in emitCOPY_FW()
3273 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitCOPY_FD() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | Thumb1FrameLowering.cpp | 117 const ThumbRegisterInfo *RegInfo = in eliminateCallFramePseudoInstr() local
135 emitCallSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount); in eliminateCallFramePseudoInstr()
138 emitCallSPUpdate(MBB, I, TII, dl, *RegInfo, Amount); in eliminateCallFramePseudoInstr()
150 const ThumbRegisterInfo *RegInfo = in emitPrologue() local
167 Register FramePtr = RegInfo->getFrameRegister(MF); in emitPrologue()
168 Register BasePtr = RegInfo->getBaseRegister(); in emitPrologue()
182 emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize, in emitPrologue()
190 emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, in emitPrologue()
405 emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes, in emitPrologue()
421 if (RegInfo->hasStackRealignment(MF)) { in emitPrologue()
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| H A D | ARMFrameLowering.cpp | 186 const ARMBaseRegisterInfo *RegInfo) { in getSpillArea() argument
214 dbgs() << "Don't know where to spill " << printReg(Reg, RegInfo) << "\n"; in getSpillArea()
336 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFPImpl() local
348 return (RegInfo->hasStackRealignment(MF) || MFI.hasVarSizedObjects() || in hasFPImpl()
438 const ARMBaseRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in insertSEH() local
502 unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in insertSEH()
516 unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); in insertSEH()
535 unsigned Reg = RegInfo->getSEHRegNum(MO.getReg()); in insertSEH()
579 unsigned Reg = RegInfo->getSEHRegNum(MO.getReg()); in insertSEH()
610 unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); in insertSEH()
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| H A D | Thumb1InstrInfo.cpp | 60 const TargetRegisterInfo *RegInfo = st.getRegisterInfo(); in copyPhysReg() local
61 LiveRegUnits UsedRegs(*RegInfo); in copyPhysReg()
73 ->addRegisterDead(ARM::CPSR, RegInfo); in copyPhysReg()
79 BitVector Allocatable = RegInfo->getAllocatableSet( in copyPhysReg()
80 MF, RegInfo->getRegClass(ARM::hGPRRegClassID)); in copyPhysReg()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineUniformityAnalysis.cpp | 72 const auto &RegInfo = F.getRegInfo(); in pushUsers() local
73 for (MachineInstr &UserInstr : RegInfo.use_instructions(Reg)) { in pushUsers()
116 const auto &RegInfo = F.getRegInfo(); in propagateTemporalDivergence() local
121 for (MachineInstr &UserInstr : RegInfo.use_instructions(Reg)) { in propagateTemporalDivergence()
141 const auto &RegInfo = F.getRegInfo(); in isDivergentUse() local
142 auto *Def = RegInfo.getOneDef(Reg); in isDivergentUse()
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| H A D | DetectDeadLanes.cpp | 216 VRegInfo &RegInfo = VRegInfos[DefRegIdx]; in transferDefinedLanesStep() local
217 LaneBitmask PrevDefinedLanes = RegInfo.DefinedLanes; in transferDefinedLanesStep()
222 RegInfo.DefinedLanes = PrevDefinedLanes | DefinedLanes; in transferDefinedLanesStep()
391 const DeadLaneDetector::VRegInfo &RegInfo) const;
425 const MachineOperand &MO, const DeadLaneDetector::VRegInfo &RegInfo) const { in isUndefRegAtInput()
428 return (RegInfo.DefinedLanes & RegInfo.UsedLanes & Mask).none(); in isUndefRegAtInput()
517 const DeadLaneDetector::VRegInfo &RegInfo = DLD.getVRegInfo(RegIdx); in modifySubRegisterOperandStatus() local
518 if (MO.isDef() && !MO.isDead() && RegInfo.UsedLanes.none()) { in modifySubRegisterOperandStatus()
526 if (isUndefRegAtInput(MO, RegInfo)) { in modifySubRegisterOperandStatus()
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| H A D | TargetRegisterInfo.cpp | 171 Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, in printRegClassOrBank() argument
173 return Printable([Reg, &RegInfo, TRI](raw_ostream &OS) { in printRegClassOrBank()
174 if (RegInfo.getRegClassOrNull(Reg)) in printRegClassOrBank()
175 OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower(); in printRegClassOrBank()
176 else if (RegInfo.getRegBankOrNull(Reg)) in printRegClassOrBank()
177 OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower(); in printRegClassOrBank()
180 assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) && in printRegClassOrBank()
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| H A D | MIRPrinter.cpp | 145 const MachineRegisterInfo &RegInfo,
264 const MachineRegisterInfo &RegInfo, in printRegClassOrBank() argument
267 OS << printRegClassOrBank(Reg, RegInfo, TRI); in printRegClassOrBank()
296 const MachineRegisterInfo &RegInfo, in convertMRI() argument
298 YamlMF.TracksRegLiveness = RegInfo.tracksLiveness(); in convertMRI()
301 for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) { in convertMRI()
305 if (RegInfo.getVRegName(Reg) != "") in convertMRI()
307 ::printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI); in convertMRI()
308 Register PreferredReg = RegInfo.getSimpleHint(Reg); in convertMRI()
316 for (std::pair<MCRegister, Register> LI : RegInfo.liveins()) { in convertMRI()
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| H A D | TargetFrameLoweringImpl.cpp | 155 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in allocateScavengingFrameIndexesNearIncomingSP() local
156 return RegInfo->useFPForScavengingIndex(MF) && in allocateScavengingFrameIndexesNearIncomingSP()
157 !RegInfo->hasStackRealignment(MF); in allocateScavengingFrameIndexesNearIncomingSP()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86CallFrameOptimization.cpp | 114 const X86RegisterInfo &RegInfo,
242 const X86RegisterInfo &RegInfo = *STI->getRegisterInfo(); in runOnMachineFunction() local
243 SlotSize = RegInfo.getSlotSize(); in runOnMachineFunction()
280 const X86RegisterInfo &RegInfo, const DenseSet<MCRegister> &UsedRegs) { in classifyInstruction() argument
340 if (RegInfo.regsOverlap(Reg, RegInfo.getStackRegister())) in classifyInstruction()
344 if (RegInfo.regsOverlap(Reg, U)) in classifyInstruction()
358 const X86RegisterInfo &RegInfo = *STI->getRegisterInfo(); in collectCallInfo() local
381 Register StackPtr = RegInfo.getStackRegister(); in collectCallInfo()
413 Classification = classifyInstruction(MBB, I, RegInfo, UsedRegs); in collectCallInfo()
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| H A D | X86MachineFunctionInfo.cpp | 40 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>( in setRestoreBasePointer() local
42 unsigned SlotSize = RegInfo->getSlotSize(); in setRestoreBasePointer()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCTLSDynamicCall.cpp | 56 MachineRegisterInfo &RegInfo = MF->getRegInfo(); in processBlock() local
178 if (!RegInfo.use_empty(OutReg)) { in processBlock()
181 for (MachineOperand &MO : RegInfo.use_operands(OutReg)) in processBlock()
201 if (RegInfo.hasOneDef(MOReg)) { in processBlock()
203 RegInfo.getOneDef(MOReg)->getParent(); in processBlock()
208 if (Temp == &MI && RegInfo.hasOneDef(InReg)) in processBlock()
209 Temp = RegInfo.getOneDef(InReg)->getParent(); in processBlock()
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| H A D | PPCFrameLowering.cpp | 312 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in determineFrameLayout() local
314 MCRegister LR = RegInfo->getRARegister(); in determineFrameLayout()
320 !RegInfo->hasBasePointer(MF) && // No special alignment. in determineFrameLayout()
394 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in replaceFPWithRealFP() local
395 bool HasBP = RegInfo->hasBasePointer(MF); in replaceFPWithRealFP()
396 unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg; in replaceFPWithRealFP()
488 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in findScratchRegister() local
489 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(MBB->getParent()); in findScratchRegister()
536 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in twoUniqueScratchRegsRequired() local
538 bool HasBP = RegInfo->hasBasePointer(MF); in twoUniqueScratchRegsRequired()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/ |
| H A D | ControlHeightReduction.cpp | 132 struct RegInfo { struct
133 RegInfo() = default;
134 RegInfo(Region *RegionIn) : R(RegionIn) {} in RegInfo() function
147 CHRScope(RegInfo RI) : BranchInsertPoint(nullptr) { in CHRScope()
200 for (RegInfo &RI : RegInfos) in addSub()
217 RegInfos, [&Boundary](const RegInfo &RI) { return Boundary == RI.R; }); in split()
220 ArrayRef<RegInfo> TailRegInfos(BoundaryIt, RegInfos.end()); in split()
222 for (const RegInfo &RI : TailRegInfos) in split()
234 [&Parent](const RegInfo &RI) { return Parent == RI.R; }) && in split()
249 for (const RegInfo &RI : RegInfos) in contains()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEFrameLowering.cpp | 311 const VERegisterInfo &RegInfo = *STI.getRegisterInfo(); in emitPrologue() local
313 bool NeedsStackRealignment = RegInfo.shouldRealignStack(MF); in emitPrologue()
319 if (NeedsStackRealignment && !RegInfo.canRealignStack(MF)) in emitPrologue()
419 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFPImpl() local
423 RegInfo->hasStackRealignment(MF) || MFI.hasVarSizedObjects() || in hasFPImpl()
445 const VERegisterInfo *RegInfo = STI.getRegisterInfo(); in getFrameIndexReference() local
456 if (RegInfo->hasStackRealignment(MF) && !isFixed) { in getFrameIndexReference()
467 FrameReg = RegInfo->getFrameRegister(MF); in getFrameIndexReference()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXInstrInfo.h | 26 const NVPTXRegisterInfo RegInfo; variable
31 const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; } in getRegisterInfo()
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| H A D | NVPTXInstrInfo.cpp | 27 NVPTXInstrInfo::NVPTXInstrInfo() : RegInfo() {} in NVPTXInstrInfo()
38 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC)) in copyPhysReg()
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| /freebsd/contrib/llvm-project/lldb/source/Plugins/Process/Utility/ |
| H A D | RegisterContextPOSIX_s390x.h | 45 struct RegInfo { struct
55 RegInfo m_reg_info; argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.cpp | 380 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in homogeneousPrologEpilog() local
381 if (MFI.hasVarSizedObjects() || RegInfo->hasStackRealignment(MF)) in homogeneousPrologEpilog()
534 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFPImpl() local
546 RegInfo->hasStackRealignment(MF)) in hasFPImpl()
1142 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in canUseAsPrologue() local
1164 if (RegInfo->hasStackRealignment(*MF) || TLI->hasInlineStackProbe(*MF)) in canUseAsPrologue()
1199 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in shouldCombineCSRLocalStackBump() local
1226 if (RegInfo->hasStackRealignment(MF)) in shouldCombineCSRLocalStackBump()
1288 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in InsertSEH() local
1295 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); in InsertSEH()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchSubtarget.h | 48 LoongArchRegisterInfo RegInfo; variable
81 return &RegInfo; in getRegisterInfo()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZLDCleanup.cpp | 132 MachineRegisterInfo &RegInfo = MF->getRegInfo(); in SetRegister() local
133 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&SystemZ::GR64BitRegClass); in SetRegister()
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