| /freebsd/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCInst.cpp | 21 void MCOperand::print(raw_ostream &OS, const MCRegisterInfo *RegInfo) const { in print()
27 if (RegInfo) in print()
28 OS << RegInfo->getName(getReg()); in print()
42 Inst->print(OS, RegInfo); in print()
75 void MCInst::print(raw_ostream &OS, const MCRegisterInfo *RegInfo) const { in print()
79 getOperand(i).print(OS, RegInfo); in print()
86 const MCRegisterInfo *RegInfo) const { in dump_pretty()
88 dump_pretty(OS, InstName, Separator, RegInfo); in dump_pretty()
92 const MCRegisterInfo *RegInfo) const { in dump_pretty()
101 getOperand(i).print(OS, RegInfo); in dump_pretty()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 93 const MipsRegisterInfo &RegInfo; member in __anonaded3df10111::ExpandPseudo
102 RegInfo(*Subtarget.getRegisterInfo()) {} in ExpandPseudo()
173 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond()
177 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0); in expandLoadCCond()
188 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond()
194 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0); in expandStoreCCond()
206 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC()
210 Register Lo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandLoadACC()
211 Register Hi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandLoadACC()
215 TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0); in expandLoadACC()
[all …]
|
| H A D | MipsSERegisterInfo.cpp | 156 const MipsRegisterInfo *RegInfo = in eliminateFI() local
183 else if (RegInfo->hasStackRealignment(MF)) { in eliminateFI()
224 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); in eliminateFI() local
225 Register Reg = RegInfo.createVirtualRegister(PtrRC); in eliminateFI()
|
| H A D | Mips16ISelDAGToDAG.cpp | 72 MachineRegisterInfo &RegInfo = MF.getRegInfo(); in initGlobalBaseReg() local
78 V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
79 V1 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
80 V2 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
|
| H A D | MipsSEISelLowering.cpp | 3030 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitBPOSGE32() local
3061 Register VR2 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32()
3067 Register VR1 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32()
3099 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitMSACBranchPseudo() local
3130 Register RD1 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo()
3136 Register RD2 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo()
3166 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitCOPY_FW() local
3177 Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass); in emitCOPY_FW()
3184 Register Wt = RegInfo.createVirtualRegister( in emitCOPY_FW()
3212 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitCOPY_FD() local
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcFrameLowering.cpp | 94 const SparcRegisterInfo &RegInfo = in emitPrologue() local
100 bool NeedsStackRealignment = RegInfo.shouldRealignStack(MF); in emitPrologue()
102 if (NeedsStackRealignment && !RegInfo.canRealignStack(MF)) in emitPrologue()
151 unsigned regFP = RegInfo.getDwarfRegNum(SP::I6, true); in emitPrologue()
164 unsigned regInRA = RegInfo.getDwarfRegNum(SP::I7, true); in emitPrologue()
165 unsigned regOutRA = RegInfo.getDwarfRegNum(SP::O7, true); in emitPrologue()
256 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFP() local
260 RegInfo->hasStackRealignment(MF) || MFI.hasVarSizedObjects() || in hasFP()
269 const SparcRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in getFrameIndexReference() local
287 } else if (RegInfo->hasStackRealignment(MF)) { in getFrameIndexReference()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineUniformityAnalysis.cpp | 71 const auto &RegInfo = F.getRegInfo(); in pushUsers() local
72 for (MachineInstr &UserInstr : RegInfo.use_instructions(Reg)) { in pushUsers()
115 const auto &RegInfo = F.getRegInfo(); in propagateTemporalDivergence() local
122 for (MachineInstr &UserInstr : RegInfo.use_instructions(Reg)) { in propagateTemporalDivergence()
140 const auto &RegInfo = F.getRegInfo(); in isDivergentUse() local
141 auto *Def = RegInfo.getOneDef(Reg); in isDivergentUse()
|
| H A D | DetectDeadLanes.cpp | 216 VRegInfo &RegInfo = VRegInfos[DefRegIdx]; in transferDefinedLanesStep() local
217 LaneBitmask PrevDefinedLanes = RegInfo.DefinedLanes; in transferDefinedLanesStep()
222 RegInfo.DefinedLanes = PrevDefinedLanes | DefinedLanes; in transferDefinedLanesStep()
401 const DeadLaneDetector::VRegInfo &RegInfo) const;
418 const MachineOperand &MO, const DeadLaneDetector::VRegInfo &RegInfo) const { in isUndefRegAtInput()
421 return (RegInfo.DefinedLanes & RegInfo.UsedLanes & Mask).none(); in isUndefRegAtInput()
510 const DeadLaneDetector::VRegInfo &RegInfo = DLD.getVRegInfo(RegIdx); in modifySubRegisterOperandStatus() local
511 if (MO.isDef() && !MO.isDead() && RegInfo.UsedLanes.none()) { in modifySubRegisterOperandStatus()
519 if (isUndefRegAtInput(MO, RegInfo)) { in modifySubRegisterOperandStatus()
|
| H A D | MachineSSAContext.cpp | |
| H A D | TargetRegisterInfo.cpp | 172 Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, in printRegClassOrBank() argument
174 return Printable([Reg, &RegInfo, TRI](raw_ostream &OS) { in printRegClassOrBank()
175 if (RegInfo.getRegClassOrNull(Reg)) in printRegClassOrBank()
176 OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower(); in printRegClassOrBank()
177 else if (RegInfo.getRegBankOrNull(Reg)) in printRegClassOrBank()
178 OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower(); in printRegClassOrBank()
181 assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) && in printRegClassOrBank()
|
| H A D | TargetFrameLoweringImpl.cpp | 152 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in allocateScavengingFrameIndexesNearIncomingSP() local
153 return RegInfo->useFPForScavengingIndex(MF) && in allocateScavengingFrameIndexesNearIncomingSP()
154 !RegInfo->hasStackRealignment(MF); in allocateScavengingFrameIndexesNearIncomingSP()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86CallFrameOptimization.cpp | 114 const X86RegisterInfo &RegInfo,
242 const X86RegisterInfo &RegInfo = in runOnMachineFunction() local
244 SlotSize = RegInfo.getSlotSize(); in runOnMachineFunction()
281 const X86RegisterInfo &RegInfo, DenseSet<unsigned int> &UsedRegs) { in classifyInstruction() argument
341 if (RegInfo.regsOverlap(Reg, RegInfo.getStackRegister())) in classifyInstruction()
345 if (RegInfo.regsOverlap(Reg, U)) in classifyInstruction()
359 const X86RegisterInfo &RegInfo = in collectCallInfo() local
383 Register StackPtr = RegInfo.getStackRegister(); in collectCallInfo()
415 Classification = classifyInstruction(MBB, I, RegInfo, UsedRegs); in collectCallInfo()
|
| H A D | X86MachineFunctionInfo.cpp | 40 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>( in setRestoreBasePointer() local
42 unsigned SlotSize = RegInfo->getSlotSize(); in setRestoreBasePointer()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCTLSDynamicCall.cpp | 60 MachineRegisterInfo &RegInfo = MF->getRegInfo(); in processBlock() local
182 if (!RegInfo.use_empty(OutReg)) { in processBlock()
185 for (MachineOperand &MO : RegInfo.use_operands(OutReg)) in processBlock()
205 if (RegInfo.hasOneDef(MOReg)) { in processBlock()
207 RegInfo.getOneDef(MOReg)->getParent(); in processBlock()
212 if (Temp == &MI && RegInfo.hasOneDef(InReg)) in processBlock()
213 Temp = RegInfo.getOneDef(InReg)->getParent(); in processBlock()
|
| H A D | PPCFrameLowering.cpp | 312 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in determineFrameLayout() local
314 unsigned LR = RegInfo->getRARegister(); in determineFrameLayout()
320 !RegInfo->hasBasePointer(MF) && // No special alignment. in determineFrameLayout()
394 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in replaceFPWithRealFP() local
395 bool HasBP = RegInfo->hasBasePointer(MF); in replaceFPWithRealFP()
396 unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg; in replaceFPWithRealFP()
488 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in findScratchRegister() local
489 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(MBB->getParent()); in findScratchRegister()
536 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in twoUniqueScratchRegsRequired() local
538 bool HasBP = RegInfo->hasBasePointer(MF); in twoUniqueScratchRegsRequired()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/ |
| H A D | ControlHeightReduction.cpp | 133 struct RegInfo { struct
134 RegInfo() = default;
135 RegInfo(Region *RegionIn) : R(RegionIn) {} in RegInfo() argument
148 CHRScope(RegInfo RI) : BranchInsertPoint(nullptr) { in CHRScope()
201 for (RegInfo &RI : RegInfos) in addSub()
218 RegInfos, [&Boundary](const RegInfo &RI) { return Boundary == RI.R; }); in split()
221 ArrayRef<RegInfo> TailRegInfos(BoundaryIt, RegInfos.end()); in split()
223 for (const RegInfo &RI : TailRegInfos) in split()
235 [&Parent](const RegInfo &RI) { return Parent == RI.R; }) && in split()
250 for (const RegInfo &RI : RegInfos) in contains()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | Thumb1FrameLowering.cpp | 119 const ThumbRegisterInfo *RegInfo = in eliminateCallFramePseudoInstr() local
137 emitCallSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount); in eliminateCallFramePseudoInstr()
140 emitCallSPUpdate(MBB, I, TII, dl, *RegInfo, Amount); in eliminateCallFramePseudoInstr()
153 const ThumbRegisterInfo *RegInfo = in emitPrologue() local
168 Register FramePtr = RegInfo->getFrameRegister(MF); in emitPrologue()
169 Register BasePtr = RegInfo->getBaseRegister(); in emitPrologue()
182 emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize, in emitPrologue()
194 emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, in emitPrologue()
429 emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes, in emitPrologue()
449 if (RegInfo->hasStackRealignment(MF)) { in emitPrologue()
[all …]
|
| H A D | ARMFrameLowering.cpp | 203 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFP() local
211 return (RegInfo->hasStackRealignment(MF) || MFI.hasVarSizedObjects() || in hasFP()
301 const ARMBaseRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in insertSEH() local
365 unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in insertSEH()
379 unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); in insertSEH()
398 unsigned Reg = RegInfo->getSEHRegNum(MO.getReg()); in insertSEH()
442 unsigned Reg = RegInfo->getSEHRegNum(MO.getReg()); in insertSEH()
473 unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); in insertSEH()
479 unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in insertSEH()
741 const ARMBaseRegisterInfo *RegInfo = STI.getRegisterInfo(); in emitPrologue() local
[all …]
|
| H A D | Thumb1InstrInfo.cpp | 59 const TargetRegisterInfo *RegInfo = st.getRegisterInfo(); in copyPhysReg() local
60 LiveRegUnits UsedRegs(*RegInfo); in copyPhysReg()
72 ->addRegisterDead(ARM::CPSR, RegInfo); in copyPhysReg()
78 BitVector Allocatable = RegInfo->getAllocatableSet( in copyPhysReg()
79 MF, RegInfo->getRegClass(ARM::hGPRRegClassID)); in copyPhysReg()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEFrameLowering.cpp | 314 const VERegisterInfo &RegInfo = *STI.getRegisterInfo(); in emitPrologue() local
316 bool NeedsStackRealignment = RegInfo.shouldRealignStack(MF); in emitPrologue()
322 if (NeedsStackRealignment && !RegInfo.canRealignStack(MF)) in emitPrologue()
422 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFP() local
426 RegInfo->hasStackRealignment(MF) || MFI.hasVarSizedObjects() || in hasFP()
448 const VERegisterInfo *RegInfo = STI.getRegisterInfo(); in getFrameIndexReference() local
459 if (RegInfo->hasStackRealignment(MF) && !isFixed) { in getFrameIndexReference()
470 FrameReg = RegInfo->getFrameRegister(MF); in getFrameIndexReference()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.cpp | 349 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in homogeneousPrologEpilog() local
350 if (MFI.hasVarSizedObjects() || RegInfo->hasStackRealignment(MF)) in homogeneousPrologEpilog()
482 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFP() local
494 RegInfo->hasStackRealignment(MF)) in hasFP()
1095 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in canUseAsPrologue() local
1119 if (!RegInfo->hasStackRealignment(*MF) && !TLI->hasInlineStackProbe(*MF)) in canUseAsPrologue()
1147 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in shouldCombineCSRLocalStackBump() local
1174 if (RegInfo->hasStackRealignment(MF)) in shouldCombineCSRLocalStackBump()
1237 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in InsertSEH() local
1246 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCInst.h | 176 void print(raw_ostream &OS, const MCRegisterInfo *RegInfo = nullptr) const;
228 void print(raw_ostream &OS, const MCRegisterInfo *RegInfo = nullptr) const;
236 const MCRegisterInfo *RegInfo = nullptr) const;
238 const MCRegisterInfo *RegInfo = nullptr) const;
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXInstrInfo.h | 26 const NVPTXRegisterInfo RegInfo; variable
31 const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; } in getRegisterInfo()
|
| /freebsd/contrib/llvm-project/lldb/source/Plugins/Process/Utility/ |
| H A D | RegisterContextPOSIX_s390x.h | 45 struct RegInfo { struct
55 RegInfo m_reg_info; argument
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaInstrInfo.cpp | 84 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); in adjustStackPtr() local
88 unsigned Reg = RegInfo.createVirtualRegister(RC); in adjustStackPtr()
158 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); in loadImmediate() local
162 *Reg = RegInfo.createVirtualRegister(RC); in loadImmediate()
|