349   const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();  in homogeneousPrologEpilog()  local
350   if (MFI.hasVarSizedObjects() || RegInfo->hasStackRealignment(MF))  in homogeneousPrologEpilog()
482   const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();  in hasFP()  local
494       RegInfo->hasStackRealignment(MF))  in hasFP()
1095   const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();  in canUseAsPrologue()  local
1119   if (!RegInfo->hasStackRealignment(*MF) && !TLI->hasInlineStackProbe(*MF))  in canUseAsPrologue()
1147   const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();  in shouldCombineCSRLocalStackBump()  local
1174   if (RegInfo->hasStackRealignment(MF))  in shouldCombineCSRLocalStackBump()
1237   const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();  in InsertSEH()  local
1246     unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());  in InsertSEH()
1247     unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg());  in InsertSEH()
1267                 .addImm(RegInfo->getSEHRegNum(Reg0))  in InsertSEH()
1268                 .addImm(RegInfo->getSEHRegNum(Reg1))  in InsertSEH()
1277     unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());  in InsertSEH()
1288     unsigned Reg =  RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());  in InsertSEH()
1297     unsigned Reg0 =  RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());  in InsertSEH()
1298     unsigned Reg1 =  RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());  in InsertSEH()
1316                 .addImm(RegInfo->getSEHRegNum(Reg0))  in InsertSEH()
1317                 .addImm(RegInfo->getSEHRegNum(Reg1))  in InsertSEH()
1324     int Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());  in InsertSEH()
1333     unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());  in InsertSEH()
1342     unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());  in InsertSEH()
1343     unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());  in InsertSEH()
1355     unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());  in InsertSEH()
1356     unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg());  in InsertSEH()
1730   const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();  in emitPrologue()  local
2023       NumBytes && !IsFunclet && RegInfo->hasStackRealignment(MF);  in emitPrologue()
2207   if (!IsFunclet && RegInfo->hasBasePointer(MF)) {  in emitPrologue()
2208     TII->copyPhysReg(MBB, MBBI, DL, RegInfo->getBaseRegister(), AArch64::SP,  in emitPrologue()
2244           *RegInfo, /*FrameReg=*/AArch64::SP, /*Reg=*/AArch64::SP, TotalSize,  in emitPrologue()
2448       const AArch64RegisterInfo &RegInfo = *Subtarget.getRegisterInfo();  in emitEpilogue()  local
2449       unsigned Reg = RegInfo.getDwarfRegNum(AArch64::SP, true);  in emitEpilogue()
2575     const AArch64RegisterInfo &RegInfo = *Subtarget.getRegisterInfo();  in emitEpilogue()  local
2576     unsigned Reg = RegInfo.getDwarfRegNum(AArch64::SP, true);  in emitEpilogue()
2690   const auto *RegInfo = static_cast<const AArch64RegisterInfo *>(  in getSEHFrameIndexOffset()  local
2693   return RegInfo->getLocalAddressRegister(MF) == AArch64::FP  in getSEHFrameIndexOffset()
2713   const auto *RegInfo = static_cast<const AArch64RegisterInfo *>(  in resolveFrameOffsetReference()  local
2742     } else if (isCSR && RegInfo->hasStackRealignment(MF)) {  in resolveFrameOffsetReference()
2748     } else if (hasFP(MF) && !RegInfo->hasStackRealignment(MF)) {  in resolveFrameOffsetReference()
2760         bool CanUseBP = RegInfo->hasBasePointer(MF);  in resolveFrameOffsetReference()
2773       } else if (MF.hasEHFunclets() && !RegInfo->hasBasePointer(MF)) {  in resolveFrameOffsetReference()
2791       ((isFixed || isCSR) || !RegInfo->hasStackRealignment(MF) || !UseFP) &&  in resolveFrameOffsetReference()
2805                       RegInfo->hasStackRealignment(MF))) {  in resolveFrameOffsetReference()
2806       FrameReg = RegInfo->getFrameRegister(MF);  in resolveFrameOffsetReference()
2810     FrameReg = RegInfo->hasBasePointer(MF) ? RegInfo->getBaseRegister()  in resolveFrameOffsetReference()
2822     FrameReg = RegInfo->getFrameRegister(MF);  in resolveFrameOffsetReference()
2827   if (RegInfo->hasBasePointer(MF))  in resolveFrameOffsetReference()
2828     FrameReg = RegInfo->getBaseRegister();  in resolveFrameOffsetReference()
3631   const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>(  in determineCalleeSaves()  local
3641   unsigned BasePointerReg = RegInfo->hasBasePointer(MF)  in determineCalleeSaves()
3642                                 ? RegInfo->getBaseRegister()  in determineCalleeSaves()
3683           !RegInfo->isReservedReg(MF, Reg)) {  in determineCalleeSaves()
3697           !RegInfo->isReservedReg(MF, PairedReg))  in determineCalleeSaves()
3759       dbgs() << ' ' << printReg(Reg, RegInfo);  in determineCalleeSaves()
3785   if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF))  in determineCalleeSaves()
3796       LLVM_DEBUG(dbgs() << "Spilling " << printReg(UnspilledCSGPR, RegInfo)  in determineCalleeSaves()
3854     MachineFunction &MF, const TargetRegisterInfo *RegInfo,  in assignCalleeSavedSpillSlots()  argument
3915     const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);  in assignCalleeSavedSpillSlots()
3933     unsigned Size = RegInfo->getSpillSize(*RC);  in assignCalleeSavedSpillSlots()
3934     Align Alignment(RegInfo->getSpillAlign(*RC));  in assignCalleeSavedSpillSlots()
4965       const AArch64RegisterInfo &RegInfo =  in inlineStackProbeFixed()  local
4967       unsigned Reg = RegInfo.getDwarfRegNum(AArch64::SP, true);  in inlineStackProbeFixed()