| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | RegisterInfoEmitter.cpp | 64 CodeGenRegBank &RegBank = Target.getRegBank(); in RegisterInfoEmitter() local
65 RegBank.computeDerivedInfo(); in RegisterInfoEmitter()
93 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
95 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
97 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
208 const CodeGenRegBank &RegBank, in EmitRegUnitPressure() argument
210 unsigned NumRCs = RegBank.getRegClasses().size(); in EmitRegUnitPressure()
211 unsigned NumSets = RegBank.getNumRegPressureSets(); in EmitRegUnitPressure()
217 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure()
219 OS << " {" << RC.getWeight(RegBank) << ", "; in EmitRegUnitPressure()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenRegisters.cpp | 79 void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) { in updateComponents() argument
88 CodeGenSubRegIndex *A = RegBank.getSubRegIdx(Comps[0]); in updateComponents()
89 CodeGenSubRegIndex *B = RegBank.getSubRegIdx(Comps[1]); in updateComponents()
90 CodeGenSubRegIndex *X = A->addComposite(B, this, RegBank.getHwModes()); in updateComponents()
103 IdxParts.push_back(RegBank.getSubRegIdx(Part)); in updateComponents()
170 void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) { in buildObjectGraph() argument
179 ExplicitSubRegIndices.push_back(RegBank.getSubRegIdx(SRIs[i])); in buildObjectGraph()
180 ExplicitSubRegs.push_back(RegBank.getReg(SRs[i])); in buildObjectGraph()
195 CodeGenRegister *Reg = RegBank.getReg(Alias); in buildObjectGraph()
264 bool CodeGenRegister::inheritRegUnits(CodeGenRegBank &RegBank) { in inheritRegUnits() argument
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| H A D | CodeGenTarget.cpp | 120 auto &RegClasses = RegBank->getRegClasses(); in getRegNamespace()
174 if (!RegBank) in getRegBank()
175 RegBank = std::make_unique<CodeGenRegBank>(Records, getHwModes()); in getRegBank()
176 return *RegBank; in getRegBank()
180 const ValueTypeByHwMode &ValueTy, CodeGenRegBank &RegBank, in getSuperRegForSubReg() argument
183 auto &RegClasses = RegBank.getRegClasses(); in getSuperRegForSubReg()
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| H A D | CodeGenTarget.h | 63 mutable std::unique_ptr<CodeGenRegBank> RegBank; variable
127 getSuperRegForSubReg(const ValueTypeByHwMode &Ty, CodeGenRegBank &RegBank,
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| H A D | CodeGenRegisters.h | 272 bool inheritRegUnits(CodeGenRegBank &RegBank);
279 unsigned getWeight(const CodeGenRegBank &RegBank) const;
422 getMatchingSubClassWithSubRegs(CodeGenRegBank &RegBank,
471 void buildRegUnitSet(const CodeGenRegBank &RegBank,
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterBankInfo.cpp | 73 const RegisterBank &RegBank = getRegBank(Idx); in verify() local
74 assert(Idx == RegBank.getID() && in verify()
76 LLVM_DEBUG(dbgs() << "Verify " << RegBank << '\n'); in verify()
77 assert(RegBank.verify(*this, TRI) && "RegBank is invalid"); in verify()
127 const RegisterBank &RegBank = getRegBankFromRegClass(*RC, MRI.getType(Reg)); in getRegBankFromConstraints() local
129 assert(RegBank.covers(*RC) && in getRegBankFromConstraints()
131 return &RegBank; in getRegBankFromConstraints()
270 const RegisterBank *RegBank) { in hashPartialMapping() argument
271 return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0); in hashPartialMapping()
278 PartMapping.RegBank); in hash_value()
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| H A D | MachineRegisterInfo.cpp | 65 const RegisterBank &RegBank) { in setRegBank() argument
66 VRegInfo[Reg].first = &RegBank; in setRegBank()
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| H A D | MachineVerifier.cpp | 2562 const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg); in visitMachineOperand() local
2566 if (!RegBank && isFunctionRegBankSelected) { in visitMachineOperand()
2574 if (RegBank && Ty.isValid() && !Ty.isScalableVector() && in visitMachineOperand()
2575 RBI->getMaximumSize(RegBank->getID()) < Ty.getSizeInBits()) { in visitMachineOperand()
2578 errs() << "Register bank " << RegBank->getName() << " too small(" in visitMachineOperand()
2579 << RBI->getMaximumSize(RegBank->getID()) << ") to fit " in visitMachineOperand()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterBankInfo.h | 61 const RegisterBank *RegBank; member
67 const RegisterBank &RegBank) in PartialMapping()
68 : StartIdx(StartIdx), Length(Length), RegBank(&RegBank) {} in PartialMapping()
472 const RegisterBank &RegBank) const;
480 const RegisterBank &RegBank) const;
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| H A D | RegisterBank.h | 83 inline raw_ostream &operator<<(raw_ostream &OS, const RegisterBank &RegBank) {
84 RegBank.print(OS);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 138 unsigned selectLoadStoreOpCode(unsigned Opc, unsigned RegBank,
191 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass() local
192 assert(RegBank && "Can't get reg bank for virtual register"); in guessRegClass()
195 assert((RegBank->getID() == ARM::GPRRegBankID || in guessRegClass()
196 RegBank->getID() == ARM::FPRRegBankID) && in guessRegClass()
199 if (RegBank->getID() == ARM::FPRRegBankID) { in guessRegClass()
358 unsigned RegBank, in selectLoadStoreOpCode() argument
362 if (RegBank == ARM::GPRRegBankID) { in selectLoadStoreOpCode()
376 if (RegBank == ARM::FPRRegBankID) { in selectLoadStoreOpCode()
1098 unsigned RegBank = RBI.getRegBank(Reg, MRI, TRI)->getID(); in select() local
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| H A D | ARMRegisterBankInfo.cpp | 52 PM.RegBank->getID() == RegBankID; in checkPartMapping()
484 (Mapping.RegBank->getID() != ARM::FPRRegBankID || in getInstrMapping()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 275 ValMapping.BreakDown[0].RegBank == ValMapping.BreakDown[1].RegBank); in getBreakDownCost()
1065 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank; in applyMappingLoad()
1339 OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank; in applyMappingSBufferLoad()
1341 OpdMapper.getInstrMapping().getOperandMapping(2).BreakDown[0].RegBank; in applyMappingSBufferLoad()
1467 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank; in applyMappingBFE()
1900 const RegisterBank &RegBank, in extendLow32IntoHigh32() argument
1912 B.getMRI()->setRegBank(ShiftAmt.getReg(0), RegBank); in extendLow32IntoHigh32()
1930 *OpdMapper.getInstrMapping().getOperandMapping(2).BreakDown[0].RegBank; in foldExtractEltToCmpSelect()
1945 *OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank; in foldExtractEltToCmpSelect()
1947 *OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank; in foldExtractEltToCmpSelect()
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| H A D | AMDGPUGenRegisterBankInfo.def | 58 // StartIdx, Length, RegBank
289 assert(BankID == ValMappings[Idx].BreakDown->RegBank->getID());
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIRParser.cpp | 631 Info.D.RegBank = nullptr; in parseRegisterInfo()
638 const RegisterBank *RegBank = Target->getRegBank(VReg.Class.Value); in parseRegisterInfo() local
639 if (!RegBank) in parseRegisterInfo()
645 Info.D.RegBank = RegBank; in parseRegisterInfo()
724 MRI.setRegBank(Reg, *Info.D.RegBank); in setupRegisterInfo()
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| H A D | MIParser.cpp | 294 const auto &RegBank = RBI->getRegBank(I); in initNames2RegBanks() local
296 std::make_pair(StringRef(RegBank.getName()).lower(), &RegBank)); in initNames2RegBanks()
1604 const RegisterBank *RegBank = nullptr; in parseRegisterClassOrBank() local
1606 RegBank = PFS.Target.getRegBank(Name); in parseRegisterClassOrBank()
1607 if (!RegBank) in parseRegisterClassOrBank()
1617 RegInfo.Kind = RegBank ? VRegInfo::REGBANK : VRegInfo::GENERIC; in parseRegisterClassOrBank()
1618 if (RegInfo.Explicit && RegInfo.D.RegBank != RegBank) in parseRegisterClassOrBank()
1620 RegInfo.D.RegBank = RegBank; in parseRegisterClassOrBank()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86GenRegisterBankInfo.def | 15 /* StartIdx, Length, RegBank */
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| H A D | X86InstructionSelector.cpp | |
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/MIRParser/ |
| H A D | MIParser.h | 46 const RegisterBank *RegBank;
44 const RegisterBank *RegBank; global() member
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64GenRegisterBankInfo.def | 15 /* StartIdx, Length, RegBank */
131 Map.RegBank == &RB;
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | RegBankSelect.cpp | 121 const RegisterBank *DesiredRegBank = ValMapping.BreakDown[0].RegBank; in assignmentMatch()
263 const RegisterBank *DesiredRegBank = ValMapping.BreakDown[0].RegBank; in getRepairCost()
611 MRI->setRegBank(Reg, *ValMapping.BreakDown[0].RegBank); in applyMapping()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 213 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); in getRegClass() local
214 return getRegClass(Ty, RegBank); in getRegClass()
1453 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectMergeValues() local
1457 MRI.setRegBank(DefReg, RegBank); in selectMergeValues()
1463 MRI.setRegBank(Tmp, RegBank); in selectMergeValues()
1522 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); in materializeFP() local
1530 getLoadStoreOp(DstTy, RegBank, TargetOpcode::G_LOAD, Alignment); in materializeFP()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCGenRegisterBankInfo.def | 16 /* StartIdx, Length, RegBank */
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.cpp | 839 *AArch64GenRegisterBankInfo::PartMappings[OpRegBankIdx[0]].RegBank, in getInstrMapping()
840 *AArch64GenRegisterBankInfo::PartMappings[OpRegBankIdx[1]].RegBank, in getInstrMapping()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.h | 168 void setRegBank(Register Reg, const RegisterBank *RegBank);
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