64     CodeGenRegBank &RegBank = Target.getRegBank();  in RegisterInfoEmitter()  local
65     RegBank.computeDerivedInfo();  in RegisterInfoEmitter()
93   void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
95   void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
97   void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
208                                               const CodeGenRegBank &RegBank,  in EmitRegUnitPressure()  argument
210   unsigned NumRCs = RegBank.getRegClasses().size();  in EmitRegUnitPressure()
211   unsigned NumSets = RegBank.getNumRegPressureSets();  in EmitRegUnitPressure()
217   for (const auto &RC : RegBank.getRegClasses()) {  in EmitRegUnitPressure()
219     OS << "    {" << RC.getWeight(RegBank) << ", ";  in EmitRegUnitPressure()
224       RC.buildRegUnitSet(RegBank, RegUnits);  in EmitRegUnitPressure()
225       OS << RegBank.getRegUnitSetWeight(RegUnits);  in EmitRegUnitPressure()
236   for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();  in EmitRegUnitPressure()
238     if (RegBank.getRegUnit(UnitIdx).Weight > 1)  in EmitRegUnitPressure()
244      << "  assert(RegUnit < " << RegBank.getNumNativeRegUnits()  in EmitRegUnitPressure()
248     for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();  in EmitRegUnitPressure()
250       const RegUnit &RU = RegBank.getRegUnit(UnitIdx);  in EmitRegUnitPressure()
273     const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);  in EmitRegUnitPressure()
289     const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);  in EmitRegUnitPressure()
301   unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists();  in EmitRegUnitPressure()
305     ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i);  in EmitRegUnitPressure()
308       PSets[i].push_back(RegBank.getRegPressureSet(PSetID).Order);  in EmitRegUnitPressure()
340      << "  assert(RegUnit < " << RegBank.getNumNativeRegUnits()  in EmitRegUnitPressure()
344   for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();  in EmitRegUnitPressure()
346     OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx])  in EmitRegUnitPressure()
687                                                    CodeGenRegBank &RegBank,  in emitComposeSubRegIndices()  argument
689   const auto &SubRegIndices = RegBank.getSubRegIndices();  in emitComposeSubRegIndices()
756     raw_ostream &OS, CodeGenRegBank &RegBank, const std::string &ClName) {  in emitComposeSubRegIndexLaneMask()  argument
758   const auto &SubRegIndices = RegBank.getSubRegIndices();  in emitComposeSubRegIndexLaneMask()
866                                     CodeGenRegBank &RegBank) {  in runMCDesc()  argument
872   const auto &Regs = RegBank.getRegisters();  in runMCDesc()
874   auto &SubRegIndices = RegBank.getSubRegIndices();  in runMCDesc()
905     Reg.addSubRegsPreOrder(SR, RegBank);  in runMCDesc()
988   for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) {  in runMCDesc()
989     ArrayRef<const CodeGenRegister *> Roots = RegBank.getRegUnit(i).getRoots();  in runMCDesc()
1000   const auto &RegisterClasses = RegBank.getRegClasses();  in runMCDesc()
1090      << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, "  in runMCDesc()
1106                                           CodeGenRegBank &RegBank) {  in runTargetHeader()  argument
1125   if (!RegBank.getSubRegIndices().empty()) {  in runTargetHeader()
1161   const auto &RegisterClasses = RegBank.getRegClasses();  in runTargetHeader()
1190                                         CodeGenRegBank &RegBank) {  in runTargetDesc()  argument
1203   const auto &RegisterClasses = RegBank.getRegClasses();  in runTargetDesc()
1204   const auto &SubRegIndices = RegBank.getSubRegIndices();  in runTargetDesc()
1440   const auto &Regs = RegBank.getRegisters();  in runTargetDesc()
1493     emitComposeSubRegIndices(OS, RegBank, ClassName);  in runTargetDesc()
1494     emitComposeSubRegIndexLaneMask(OS, RegBank, ClassName);  in runTargetDesc()
1548             MatchingSubClass = RC.getMatchingSubClassWithSubRegs(RegBank, &Idx);  in runTargetDesc()
1576   EmitRegUnitPressure(OS, RegBank, ClassName);  in runTargetDesc()
1652   printMask(OS, RegBank.CoveringLanes);  in runTargetDesc()
1658      << "                     " << RegBank.getNumNativeRegUnits() << ",\n"  in runTargetDesc()
1676     const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);  in runTargetDesc()
1686     BitVector Covered = RegBank.computeCoveredRegisters(*Regs);  in runTargetDesc()
1693       RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc());  in runTargetDesc()
1694       Covered |= RegBank.computeCoveredRegisters(  in runTargetDesc()
1700     for (auto &Reg : RegBank.getRegisters()) {  in runTargetDesc()
1704     Covered |= RegBank.computeCoveredRegisters(  in runTargetDesc()
1727       RegBank.getRegCategories();  in runTargetDesc()
1804   CodeGenRegBank &RegBank = Target.getRegBank();  in run()  local
1806   runEnums(OS, Target, RegBank);  in run()
1809   runMCDesc(OS, Target, RegBank);  in run()
1812   runTargetHeader(OS, Target, RegBank);  in run()
1815   runTargetDesc(OS, Target, RegBank);  in run()
1822   CodeGenRegBank &RegBank = Target.getRegBank();  in debugDump()  local
1831   for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) {  in debugDump()
1853     for (const CodeGenRegisterClass &SRC : RegBank.getRegClasses()) {  in debugDump()
1866   for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) {  in debugDump()
1879   for (const CodeGenRegister &R : RegBank.getRegisters()) {  in debugDump()