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Searched refs:RSP (Results 1 – 25 of 30) sorted by relevance

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/freebsd/sys/amd64/amd64/
H A Dbpf_jit_machdep.c205 MOVrq(RSP, RBP); in bpf_jit_compile()
206 SUBib(BPF_MEMWORDS * sizeof(uint32_t), RSP); in bpf_jit_compile()
399 MOVobd(RSP, RSI, EAX); in bpf_jit_compile()
404 MOVobd(RSP, RSI, EDX); in bpf_jit_compile()
414 MOVomd(EAX, RSP, RSI); in bpf_jit_compile()
419 MOVomd(EDX, RSP, RSI); in bpf_jit_compile()
H A Dbpf_jit_machdep.h44 #define RSP 4 macro
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DFixupStatepointCallerSaved.cpp190 RegSlotPair RSP(Reg, FI); in tryRecordReload() local
191 return Reloads[MBB].insert(RSP).second; in tryRecordReload()
255 Vec, [Reg](RegSlotPair &RSP) { return Reg == RSP.first; }); in getFrameIndex() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrControl.td317 // RSP is marked as a use to prevent stack-pointer assignments that appear
320 let isCall = 1, Uses = [RSP, SSP], SchedRW = [WriteJump] in {
353 isCodeGenOnly = 1, Uses = [RSP, SSP] in {
391 Uses = [RSP, SSP],
412 Uses = [RSP, SSP],
435 let Uses = [RSP, EFLAGS, SSP] in {
H A DX86RegisterInfo.td290 def RSP : X86Reg<"rsp", 4, [ESP]>, DwarfRegNum<[7, -2, -2]>;
594 R14, R15, R12, R13, R20, R21, R28, R29, RBP, RSP, RIP)>;
596 // GR64PLTSafe - 64-bit GPRs without R10, R11, RSP and RIP. Could be used when
638 R8, R9, R11, RIP, RSP)>;
641 RIP, RSP)>;
659 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
685 // GR64_NOSP - GR64 registers except RSP (and RIP).
686 def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)>;
693 // GR64_NOREX_NOSP - GR64_NOREX registers except RSP.
701 // GR64_NOREX2_NOSP - GR64_NOREX2 registers except RSP, RIP.
[all …]
H A DX86LoadValueInjectionRetHardening.cpp98 X86::RSP, false, 0) in runOnMachineFunction()
H A DX86FrameLowering.cpp1048 addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false, in emitStackProbeInlineWindowsCoreCLR64()
1052 addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false, in emitStackProbeInlineWindowsCoreCLR64()
1065 BuildMI(&MBB, DL, TII.get(X86::MOV64rr), CopyReg).addReg(X86::RSP); in emitStackProbeInlineWindowsCoreCLR64()
1142 X86::RSP, false, RCXShadowSlot); in emitStackProbeInlineWindowsCoreCLR64()
1146 X86::RSP, false, RDXShadowSlot); in emitStackProbeInlineWindowsCoreCLR64()
1151 BuildMI(*ContinueMBB, ContinueMBBI, DL, TII.get(X86::SUB64rr), X86::RSP) in emitStackProbeInlineWindowsCoreCLR64()
1152 .addReg(X86::RSP) in emitStackProbeInlineWindowsCoreCLR64()
1225 unsigned SP = Uses64BitFramePtr ? X86::RSP : X86::ESP; in emitStackProbeCall()
1863 .addUse(X86::RSP) in emitPrologue()
1869 BuildMI(MBB, MBBI, DL, TII.get(X86::SUB64ri32), X86::RSP) in emitPrologue()
[all …]
H A DX86IndirectThunks.cpp229 const Register SPReg = Is64Bit ? X86::RSP : X86::ESP; in populateThunk()
H A DX86RegisterInfo.cpp76 StackPtr = Use64BitReg ? X86::RSP : X86::ESP; in X86RegisterInfo()
554 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RSP)) in getReservedRegs()
727 if (TRI.isSuperOrSubRegisterEq(X86::RSP, PhysReg)) in isFixedRegister()
1018 if (!Uses.count(CS) && CS != X86::RIP && CS != X86::RSP && CS != X86::ESP) in findDeadCallerSavedReg()
H A DX86SpeculativeLoadHardening.cpp1532 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(X86::OR64rr), X86::RSP) in mergePredStateIntoSP()
1533 .addReg(X86::RSP) in mergePredStateIntoSP()
1550 .addReg(X86::RSP); in extractPredStateFromSP()
1579 } else if (BaseMO.getReg() == X86::RSP) { in hardenLoadAddr()
2141 .addReg(/*Base*/ X86::RSP) in tracePredStateThroughCall()
H A DX86InstrMisc.td45 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in
122 let Uses = [RSP] in
135 let Defs = [RSP, EFLAGS, DF], Uses = [RSP] in
155 let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in {
200 let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1,
210 let Defs = [RSP, EFLAGS, DF], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
213 let Defs = [RSP], Uses = [RSP, EFLAGS, DF], mayStore = 1, hasSideEffects=0 in
H A DX86InstrCompiler.td52 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
57 let Defs = [RSP, EFLAGS, SSP], Uses = [RSP, SSP], SchedRW = [WriteALU] in {
112 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
129 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
156 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
498 // All calls clobber the non-callee saved registers. RSP is marked as
507 Uses = [RSP, SSP] in {
529 let Defs = [EAX, EFLAGS], Uses = [RSP, SSP] in {
554 Uses = [RSP, SSP],
H A DX86InstrOperands.td9 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
H A DX86FixupLEAs.cpp569 if (UseLEAForSP && (DestReg == X86::ESP || DestReg == X86::RSP)) in optTwoAddrLEA()
H A DX86InstrSystem.td73 let hasSideEffects = 1, Defs = [RSP, EFLAGS] in {
78 } // hasSideEffects = 1, Defs = [RSP, EFLAGS]
H A DX86InstrInfo.cpp10665 if (MI.modifiesRegister(X86::RSP, &RI) || MI.readsRegister(X86::RSP, &RI) || in getOutliningTypeImpl()
10666 MI.getDesc().hasImplicitUseOfPhysReg(X86::RSP) || in getOutliningTypeImpl()
10667 MI.getDesc().hasImplicitDefOfPhysReg(X86::RSP)) in getOutliningTypeImpl()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp263 {codeview::RegisterId::RSP, X86::RSP}, in initLLVMToSEHAndCVRegMapping()
466 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP; in createX86MCAsmInfo()
786 #define SP_SUB_SUPER(R) SUB_SUPER(SPL, SP, ESP, RSP, R) in getX86SubSuperRegister()
924 SP_SUB_SUPER(RSP) in getX86SubSuperRegister()
H A DX86BaseInfo.h1338 case X86::RSP: in needSIB()
H A DX86MCCodeEmitter.cpp839 assert(IndexReg.getReg() != X86::ESP && IndexReg.getReg() != X86::RSP && in emitMemModRMByte()
/freebsd/contrib/llvm-project/llvm/lib/DebugInfo/CodeView/
H A DSymbolRecordMapping.cpp531 case EncodedFramePtrReg::StackPtr: return RegisterId::RSP; in decodeFramePtrReg()
566 case RegisterId::RSP: in encodeFramePtrReg()
/freebsd/contrib/llvm-project/lldb/source/Plugins/SymbolFile/NativePDB/
H A DCodeViewRegisterMapping.cpp718 case llvm::codeview::RegisterId::RSP: in GetRegisterSize()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h326 ENTRY(RSP) \
/freebsd/contrib/llvm-project/llvm/include/llvm/DebugInfo/CodeView/
H A DCodeViewRegisters.def228 CV_REGISTER(RSP, 335)
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp1356 IndexReg == X86::RSP) { in CheckBaseRegAndIndexRegAndScale()
2684 if (Scale == 0 && BaseReg != X86::ESP && BaseReg != X86::RSP && in parseIntelOperand()
2685 (IndexReg == X86::ESP || IndexReg == X86::RSP)) in parseIntelOperand()
4050 is64BitMode() ? X86::RSP : (Parse32 ? X86::ESP : X86::SP); in applyLVICFIMitigation()
/freebsd/crypto/openssl/Configurations/
H A Dwindows-makefile.tmpl723 # in handling quoted paths: https://quality.embarcadero.com/browse/RSP-31756

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