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Searched refs:REV16 (Results 1 – 11 of 11) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedCyclone.td152 // CLS,CLZ,RBIT,REV,REV16,REV32
504 // CLS,CLZ,CNT,RBIT,REV16,REV32,REV64,XTN
H A DAArch64ISelLowering.h217 REV16, enumerator
H A DAArch64SchedAmpere1.td992 (instregex "(RBIT|REV|REV16)(W|X)r", "REV32Xr")>;
H A DAArch64SchedAmpere1B.td974 (instregex "(RBIT|REV|REV16)(W|X)r", "REV32Xr")>;
H A DAArch64SchedFalkorDetails.td1207 def : InstRW<[FalkorWr_1XYZ_2cyc], (instregex "^(CLS|CLZ|RBIT|REV|REV16|REV32)(W|X)r$")>;
H A DAArch64ISelLowering.cpp2640 MAKE_CASE(AArch64ISD::REV16) in getTargetNodeName()
12800 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS); in GeneratePerfectShuffle()
13209 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2); in LowerVECTOR_SHUFFLE()
H A DAArch64InstrInfo.td759 def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDT_AArch64UnaryVec>;
5356 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", AArch64rev16>;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleR52.td338 (instregex "t2LDC", "RBIT", "REV", "REV16", "REVSH", "RRX")>;
H A DARMScheduleSwift.td131 // CLZ,RBIT,REV,REV16,REVSH,PKH
H A DARMInstrInfo.td4777 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4784 (REV16 (LDRH addrmode3:$addr))>;
4786 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>;
4788 (REV16 GPR:$Rn)>;
H A DARMInstrThumb2.td5196 // Alias for REV/REV16/REVSH without the ".w" optional width specifier.