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Searched refs:READ4 (Results 1 – 25 of 44) sorted by relevance

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/freebsd/sys/dev/dwc/
H A Ddwc1000_core.c106 if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) { in dwc1000_miibus_read_reg()
107 rv = READ4(sc, GMII_DATA); in dwc1000_miibus_read_reg()
134 if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) { in dwc1000_miibus_write_reg()
166 reg = READ4(sc, MAC_CONFIGURATION); in dwc1000_miibus_statchg()
215 reg = READ4(sc, MAC_CONFIGURATION); in dwc1000_core_setup()
226 reg = READ4(sc, MAC_CONFIGURATION); in dwc1000_enable_mac()
240 reg = READ4(sc, MAC_CONFIGURATION); in dwc1000_enable_csum_offload()
368 lo = READ4(sc, MAC_ADDRESS_LOW(0)); in dwc1000_get_hwaddr()
369 hi = READ4(sc, MAC_ADDRESS_HIGH(0)) & 0xffff; in dwc1000_get_hwaddr()
397 reg = READ4(sc, MMC_CONTROL); in dwc1000_clear_stats()
[all …]
/freebsd/sys/arm/freescale/imx/
H A Dimx_gpt.c52 #define READ4(_sc, _r) \ macro
55 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m))
57 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m))
213 while (READ4(sc, IMX_GPT_CR) & GPT_CR_SWR) in imx_gpt_attach()
235 sc->clkfreq / 1000, basefreq, READ4(sc, IMX_GPT_CR), READ4(sc, IMX_GPT_PR)); in imx_gpt_attach()
254 t1 = READ4(sc, IMX_GPT_CNT); in imx_gpt_attach()
256 t2 = READ4(sc, IMX_GPT_CNT); in imx_gpt_attach()
295 WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) + sc->sc_period); in imx_gpt_timer_start()
310 WRITE4(sc, IMX_GPT_OCR3, READ4(sc, IMX_GPT_CNT) + ticks); in imx_gpt_timer_start()
343 status = READ4(sc, IMX_GPT_SR); in imx_gpt_intr()
[all …]
H A Dimx_gpio.c73 #define READ4(_sc, _r) \ macro
76 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m))
78 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m))
380 wrk = READ4(sc, reg); in gpio_pic_setup_intr()
470 interrupts = READ4(sc, IMX_GPIO_ISR_REG) & READ4(sc, IMX_GPIO_IMR_REG); in gpio_pic_filter()
549 pad = READ4(sc, IMX_GPIO_PSR_REG); in imx51_gpio_pin_configure()
551 pad = READ4(sc, IMX_GPIO_DR_REG); in imx51_gpio_pin_configure()
690 *val = (READ4(sc, IMX_GPIO_PSR_REG) >> pin) & 1; in imx51_gpio_pin_get()
692 *val = (READ4(sc, IMX_GPIO_DR_REG) >> pin) & 1; in imx51_gpio_pin_get()
709 (READ4(sc, IMX_GPIO_DR_REG) ^ (1U << pin))); in imx51_gpio_pin_toggle()
[all …]
H A Dimx6_sdma.c62 #define READ4(_sc, _reg) \ macro
94 pending = READ4(sc, SDMAARM_INTR); in sdma_intr()
214 reg = READ4(sc, SDMAARM_EVTOVR); in sdma_overrides()
222 reg = READ4(sc, SDMAARM_HOSTOVR); in sdma_overrides()
230 reg = READ4(sc, SDMAARM_DSPOVR); in sdma_overrides()
333 while (!(ret = READ4(sc, SDMAARM_INTR) & 1)) { in sdma_configure()
442 while (!(ret = READ4(sc, SDMAARM_INTR) & 1)) { in boot_firmware()
/freebsd/sys/arm/freescale/vybrid/
H A Dvf_anadig.c134 reg = READ4(sc, pll_ctrl); in enable_pll()
143 while (!(READ4(sc, pll_ctrl) & ANADIG_PLL_LOCKED)) in enable_pll()
146 reg = READ4(sc, pll_ctrl); in enable_pll()
165 reg = READ4(sc, ANADIG_PLL4_CTRL); in pll4_configure_output()
206 reg = READ4(sc, ANADIG_REG_3P0); in anadig_attach()
211 reg = READ4(sc, USB_MISC(0)); in anadig_attach()
215 reg = READ4(sc, USB_MISC(1)); in anadig_attach()
221 READ4(sc, USB_ANALOG_USB_MISC(0))); in anadig_attach()
223 READ4(sc, USB_ANALOG_USB_MISC(1))); in anadig_attach()
H A Dvf_spi.c160 reg = READ4(sc, SPI_MCR); in spi_attach()
168 reg = READ4(sc, SPI_RSER); in spi_attach()
172 reg = READ4(sc, SPI_MCR); in spi_attach()
176 reg = READ4(sc, SPI_CTAR0); in spi_attach()
194 reg = READ4(sc, SPI_CTAR0); in spi_attach()
229 while((READ4(sc, SPI_SR) & SR_EOQF) == 0) in spi_txrx()
232 reg = READ4(sc, SPI_SR); in spi_txrx()
238 while((READ4(sc, SPI_SR) & SR_RFDF) == 0) in spi_txrx()
H A Dvf_adc.c155 return (READ4(sc, ADC_R0)); in adc_read()
168 reg = READ4(sc, ADC_HC0); in adc_enable()
205 reg = READ4(sc, ADC_CFG); in adc_attach()
211 reg = READ4(sc, ADC_GC); in adc_attach()
216 reg = READ4(sc, ADC_HC0); in adc_attach()
H A Dvf_edma.c100 interrupts = READ4(sc, DMA_INT); in edma_transfer_complete_intr()
125 /* reg = */ READ4(sc, DMA_ERR); in edma_err_intr()
129 reg, READ4(sc, DMA_ES)); in edma_err_intr()
198 reg = READ4(sc, DMA_ERQ); in dma_stop()
245 reg = READ4(sc, DMA_ERQ); in dma_setup()
250 reg = READ4(sc, DMA_EEI); in dma_setup()
H A Dvf_sai.c355 reg = READ4(sc, I2S_TCR2); in sai_configure_clock()
609 READ4(sc, I2S_TCSR)); in sai_intr()
621 reg = READ4(sc, I2S_TCSR); in setup_sai()
625 reg = READ4(sc, I2S_TCR3); in setup_sai()
632 reg = READ4(sc, I2S_TCR2); in setup_sai()
640 reg = READ4(sc, I2S_TCR3); in setup_sai()
645 reg = READ4(sc, I2S_TCR4); in setup_sai()
653 reg = READ4(sc, I2S_TCR5); in setup_sai()
663 reg = READ4(sc, I2S_TCSR); in setup_sai()
/freebsd/sys/dev/clk/rockchip/
H A Drk_clk_pll.c55 #define READ4(_clk, off, val) \ macro
128 READ4(clk, sc->mode_reg, &reg); in rk3066_clk_pll_init()
167 READ4(clk, sc->base_offset, &raw0); in rk3066_clk_pll_recalc()
168 READ4(clk, sc->base_offset + 4, &raw1); in rk3066_clk_pll_recalc()
169 READ4(clk, sc->base_offset + 8, &raw2); in rk3066_clk_pll_recalc()
170 READ4(clk, sc->mode_reg, &reg); in rk3066_clk_pll_recalc()
250 READ4(clk, sc->base_offset + 4, &reg); in rk3066_clk_pll_set_freq()
270 READ4(clk, sc->base_offset + 0x4, &reg); in rk3066_clk_pll_set_freq()
389 READ4(clk, sc->base_offset, &raw1); in rk3328_clk_pll_recalc()
390 READ4(clk, sc->base_offset + 4, &raw2); in rk3328_clk_pll_recalc()
[all …]
/freebsd/sys/arm64/freescale/imx/clk/
H A Dimx_clk_frac_pll.c44 #define READ4(_clk, off, val) \ macro
90 READ4(clk, sc->offset + CFG0, &cfg0); in imx_clk_frac_pll_set_gate()
100 READ4(clk, sc->offset + CFG0, &cfg0); in imx_clk_frac_pll_set_gate()
122 READ4(clk, sc->offset + CFG0, &cfg0); in imx_clk_frac_pll_recalc()
123 READ4(clk, sc->offset + CFG1, &cfg1); in imx_clk_frac_pll_recalc()
H A Dimx_clk_sscg_pll.c44 #define READ4(_clk, off, val) \ macro
99 READ4(clk, sc->offset + CFG0, &cfg0); in imx_clk_sscg_pll_set_gate()
109 READ4(clk, sc->offset + CFG0, &cfg0); in imx_clk_sscg_pll_set_gate()
131 READ4(clk, sc->offset + CFG0, &cfg0); in imx_clk_sscg_pll_recalc()
132 READ4(clk, sc->offset + CFG2, &cfg2); in imx_clk_sscg_pll_recalc()
H A Dimx_clk_composite.c58 #define READ4(_clk, off, val) \ macro
83 READ4(clk, sc->offset, &val); in imx_clk_composite_init()
102 READ4(clk, sc->offset, &val); in imx_clk_composite_set_gate()
123 READ4(clk, sc->offset, &val); in imx_clk_composite_set_mux()
141 READ4(clk, sc->offset, &reg); in imx_clk_composite_recalc()
266 READ4(clk, sc->offset, &val); in imx_clk_composite_set_freq()
/freebsd/sys/dev/mmc/host/
H A Ddwmmc.c88 #define READ4(_sc, _reg) \ macro
214 reg = READ4(sc, SDMMC_CTRL); in dwmmc_ctrl_reset()
220 if (!(READ4(sc, SDMMC_CTRL) & reset_bits)) in dwmmc_ctrl_reset()
335 cmd->resp[3] = READ4(sc, SDMMC_RESP0); in dwmmc_cmd_done()
336 cmd->resp[2] = READ4(sc, SDMMC_RESP1); in dwmmc_cmd_done()
337 cmd->resp[1] = READ4(sc, SDMMC_RESP2); in dwmmc_cmd_done()
338 cmd->resp[0] = READ4(sc, SDMMC_RESP3); in dwmmc_cmd_done()
343 cmd->resp[0] = READ4(sc, SDMMC_RESP0); in dwmmc_cmd_done()
388 reg = READ4(sc, SDMMC_MINTSTS); in dwmmc_intr()
421 READ4(sc, SDMMC_CDETECT) == 0 ? true : false); in dwmmc_intr()
[all …]
/freebsd/sys/arm/ti/clk/
H A Dti_clk_clkctrl.c72 #define READ4(_clk, off, val) \ macro
100 READ4(clk, sc->register_offset, &val); in ti_clkctrl_set_gdbclk_gate()
118 READ4(clk, sc->register_offset, &val); in ti_clkctrl_set_gdbclk_gate()
150 READ4(clk, sc->register_offset, &val); in ti_clkctrl_set_gate()
158 READ4(clk, sc->register_offset, &val); in ti_clkctrl_set_gate()
/freebsd/sys/dev/xilinx/
H A Daxi_quad_spi.c64 #define READ4(_sc, _reg) \ macro
166 while(!(READ4(sc, SPI_SR) & SR_TX_EMPTY)) in spi_txrx()
169 data = READ4(sc, SPI_DRR); in spi_txrx()
197 reg = READ4(sc, SPI_SSR); in spi_transfer()
208 reg = READ4(sc, SPI_SSR); in spi_transfer()
H A Daxidma.c62 #define READ4(_sc, _reg) \ macro
154 pending = READ4(sc, AXI_DMASR(data->id)); in axidma_intr()
162 READ4(sc, AXI_DMASR(data->id))); in axidma_intr()
164 READ4(sc, AXI_CURDESC(data->id))); in axidma_intr()
166 READ4(sc, AXI_TAILDESC(data->id))); in axidma_intr()
227 if ((READ4(sc, AXI_DMACR(chan_id)) & DMACR_RESET) == 0) in axidma_reset()
237 __func__, READ4(sc, AXI_DMACR(chan_id))); in axidma_reset()
507 READ4(sc, AXI_DMASR(data->id))); in axidma_channel_submit_sg()
561 reg = READ4(sc, AXI_DMACR(data->id)); in axidma_channel_prep_sg()
/freebsd/sys/dev/gpio/dwgpio/
H A Ddwgpio.c64 #define READ4(_sc, _reg) DWGPIO_READ((_sc)->parent, _reg) macro
151 version = READ4(sc, GPIO_VER_ID_CODE); in dwgpio_attach()
156 cfg2 = READ4(sc, GPIO_CONFIG_REG2); in dwgpio_attach()
165 (READ4(sc, GPIO_SWPORT_DDR(sc->port)) & (1 << i)) ? in dwgpio_attach()
283 *val = (READ4(sc, GPIO_EXT_PORT(sc->port)) & (1 << i)) ? 1 : 0; in dwgpio_pin_get()
306 reg = READ4(sc, GPIO_SWPORT_DR(sc->port)); in dwgpio_pin_toggle()
330 reg = READ4(sc, GPIO_SWPORT_DDR(sc->port)); in dwgpio_pin_configure()
385 reg = READ4(sc, GPIO_SWPORT_DR(sc->port)); in dwgpio_pin_set()
/freebsd/sys/dev/flash/
H A Dcqspi.c80 #define READ4(_sc, _reg) bus_read_4((_sc)->res[0], _reg) macro
150 pending = READ4(sc, CQSPI_IRQSTAT); in cqspi_intr()
237 if ((READ4(sc, CQSPI_FLASHCMD) & FLASHCMD_CMDEXECSTAT) == 0) { in cqspi_wait_for_completion()
244 __func__, READ4(sc, CQSPI_FLASHCMD)); in cqspi_wait_for_completion()
325 data = READ4(sc, CQSPI_FLASHCMDRDDATALO); in cqspi_cmd_read()
379 reg = READ4(sc, CQSPI_CFG); in cqspi_wait_idle()
526 READ4(sc, CQSPI_MODULEID)); in cqspi_init()
551 reg = READ4(sc, CQSPI_CFG); in cqspi_init()
555 reg = READ4(sc, CQSPI_DEVSZ); in cqspi_init()
564 reg = READ4(sc, CQSPI_CFG); in cqspi_init()
[all …]
/freebsd/sys/dev/clk/allwinner/
H A Daw_clk_nkmp.c64 #define READ4(_clk, off, val) \ macro
84 READ4(clk, sc->offset, &val); in aw_clk_nkmp_init()
106 READ4(clk, sc->offset, &val); in aw_clk_nkmp_set_gate()
129 READ4(clk, sc->offset, &val); in aw_clk_nkmp_set_mux()
197 READ4(clk, sc->offset, &val); in aw_clk_nkmp_set_freq_scale()
239 READ4(clk, sc->offset, &val); in aw_clk_nkmp_set_freq_scale()
284 READ4(clk, sc->offset, &val); in aw_clk_nkmp_set_freq()
299 READ4(clk, sc->offset, &val); in aw_clk_nkmp_set_freq()
308 READ4(clk, sc->offset, &val); in aw_clk_nkmp_set_freq()
331 READ4(clk, sc->offset, &val); in aw_clk_nkmp_recalc()
H A Daw_clk_m.c61 #define READ4(_clk, off, val) \ macro
79 READ4(clk, sc->offset, &val); in aw_clk_m_init()
101 READ4(clk, sc->offset, &val); in aw_clk_m_set_gate()
124 READ4(clk, sc->offset, &val); in aw_clk_m_set_mux()
207 READ4(clk, sc->offset, &val); in aw_clk_m_set_freq()
231 READ4(clk, sc->offset, &val); in aw_clk_m_recalc()
H A Daw_clk_nm.c62 #define READ4(_clk, off, val) \ macro
80 READ4(clk, sc->offset, &val); in aw_clk_nm_init()
102 READ4(clk, sc->offset, &val); in aw_clk_nm_set_gate()
125 READ4(clk, sc->offset, &val); in aw_clk_nm_set_mux()
237 READ4(clk, sc->offset, &val); in aw_clk_nm_set_freq()
251 READ4(clk, sc->offset, &val); in aw_clk_nm_set_freq()
273 READ4(clk, sc->offset, &val); in aw_clk_nm_recalc()
H A Daw_clk_np.c61 #define READ4(_clk, off, val) \ macro
88 READ4(clk, sc->offset, &val); in aw_clk_np_set_gate()
164 READ4(clk, sc->offset, &val); in aw_clk_np_set_freq()
178 READ4(clk, sc->offset, &val); in aw_clk_np_set_freq()
200 READ4(clk, sc->offset, &val); in aw_clk_np_recalc()
H A Daw_clk_frac.c69 #define READ4(_clk, off, val) \ macro
87 READ4(clk, sc->offset, &val); in aw_clk_frac_init()
111 READ4(clk, sc->offset, &val); in aw_clk_frac_set_gate()
135 READ4(clk, sc->offset, &val); in aw_clk_frac_set_mux()
264 READ4(clk, sc->offset, &val); in aw_clk_frac_set_freq()
296 READ4(clk, sc->offset, &val); in aw_clk_frac_set_freq()
317 READ4(clk, sc->offset, &val); in aw_clk_frac_recalc()
H A Daw_clk_prediv_mux.c60 #define READ4(_clk, off, val) \ macro
78 READ4(clk, sc->offset, &val); in aw_clk_prediv_mux_init()
97 READ4(clk, sc->offset, &val); in aw_clk_prediv_mux_set_mux()
115 READ4(clk, sc->offset, &val); in aw_clk_prediv_mux_recalc()

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