88 #define	READ4(_sc, _reg) \  macro
214 	reg = READ4(sc, SDMMC_CTRL);  in dwmmc_ctrl_reset()
220 		if (!(READ4(sc, SDMMC_CTRL) & reset_bits))  in dwmmc_ctrl_reset()
326 			cmd->resp[3] = READ4(sc, SDMMC_RESP0);  in dwmmc_cmd_done()
327 			cmd->resp[2] = READ4(sc, SDMMC_RESP1);  in dwmmc_cmd_done()
328 			cmd->resp[1] = READ4(sc, SDMMC_RESP2);  in dwmmc_cmd_done()
329 			cmd->resp[0] = READ4(sc, SDMMC_RESP3);  in dwmmc_cmd_done()
334 			cmd->resp[0] = READ4(sc, SDMMC_RESP0);  in dwmmc_cmd_done()
382 	reg = READ4(sc, SDMMC_MINTSTS);  in dwmmc_intr()
415 			    READ4(sc, SDMMC_CDETECT) == 0 ? true : false);  in dwmmc_intr()
431 		reg = READ4(sc, SDMMC_IDSTS);  in dwmmc_intr()
475 	if (READ4(sc, SDMMC_CDETECT) == 0 ||  in dwmmc_card_task()
693 		READ4(sc, SDMMC_VERID) & 0xffff);  in dwmmc_attach()
705 		    ((READ4(sc, SDMMC_FIFOTH) >> SDMMC_FIFOTH_RXWMARK_S) & 0xfff);  in dwmmc_attach()
823 		} while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START);  in dwmmc_setup_bus()
843 	} while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START);  in dwmmc_setup_bus()
855 	} while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START);  in dwmmc_setup_bus()
900 	reg = READ4(sc, SDMMC_UHS_REG);  in dwmmc_update_ios()
944 	reg = READ4(sc, SDMMC_CTRL);  in dma_stop()
949 	reg = READ4(sc, SDMMC_BMOD);  in dma_stop()
966 	reg = READ4(sc, SDMMC_INTMASK);  in dma_prepare()
994 	reg = READ4(sc, SDMMC_CTRL);  in dma_prepare()
999 	reg = READ4(sc, SDMMC_BMOD);  in dma_prepare()
1045 		status = READ4(sc, SDMMC_STATUS);  in pio_read()
1048 		*p++ = READ4(sc, SDMMC_DATA);  in pio_read()
1072 		status = READ4(sc, SDMMC_STATUS);  in pio_write()
1209 	while (READ4(sc, SDMMC_STATUS) & (SDMMC_STATUS_DATA_BUSY))  in dwmmc_next_operation()