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/freebsd/contrib/llvm-project/libc/src/__support/OSUtil/linux/arm/
H A Dsyscall.h16 #define R7 long r7 = number macro
29 #define R7 register long r7 asm("r7") = number macro
35 R7; \
38 R7; \
/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/hexagon/
H A Dfastmath_dlib_asm.S65 #define mantexpd R7:6
72 #define zero R7:6
200 #define mantexpd R7:6
207 #define zero R7:6
329 #define mantexpd R7:6
334 #define zero0 R7:6
H A Dfastmath2_dlib_asm.S63 #define mantexpd R7:6
164 #define mantexpd R7:6
266 #define mantexpd R7:6
267 #define mantdh R7
378 #define c07f R7
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.cpp39 MSP430::R4, MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
44 MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
49 MSP430::R4, MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
55 MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
H A DMSP430RegisterInfo.td62 def R7 : MSP430RegWithSubregs<7, "r7", [R7B]>, DwarfRegNum<[7]>;
83 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.td32 def R7 : Ri< 7, "r7">, DwarfRegNum<[7]>;
48 R4, R5, R6, R7, R8, R9, R10,
55 R4, R5, R6, R7, R8, R9, R10,
H A DXCoreRegisterInfo.cpp212 XCore::R4, XCore::R5, XCore::R6, XCore::R7, in getCalleeSavedRegs()
217 XCore::R4, XCore::R5, XCore::R6, XCore::R7, in getCalleeSavedRegs()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallingConv.td122 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
275 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
282 // PrologEpilogInserter to allocate frame index slots. So when R7 is the frame
284 def CSR_ATPCS_SplitPush : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
288 def CSR_Win_SplitFP : CalleeSavedRegs<(add R10, R9, R8, R7, R6, R5, R4,
297 def CSR_Win_AAPCS_CFGuard_Check : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7,
319 def CSR_AAPCS_SplitPush_R11 : CalleeSavedRegs<(add R10, R9, R8, R7, R6, R5, R4,
323 R7, R6, R5, R4,
331 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
336 // Also save R7-R4 first to match the stack frame fixed spill areas.
[all …]
H A DARMSLSHardening.cpp141 {"__llvm_slsblr_thunk_arm_r7", ARM::R7, false},
155 {"__llvm_slsblr_thunk_thumb_r7", ARM::R7, true},
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.cpp73 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_AlignArgRegs()
98 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
149 static const MCPhysReg HiRegList[] = { PPC::R3, PPC::R5, PPC::R7, PPC::R9 }; in CC_PPC32_SPE_CustomSplitFP64()
H A DPPCCallingConv.td76 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
87 CCIfType<[f32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>,
221 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
236 CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>,
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiCallingConv.td24 CCAssignToReg<[R6, R7, R18, R19]>>>>,
36 CCIfNotVarArg<CCIfType<[i32], CCAssignToReg<[ R6, R7, R18, R19 ]>>>,
H A DLanaiRegisterInfo.td48 R6, R7, R18, R19, // registers for passing arguments
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFCallingConv.td48 def CSR : CalleeSavedRegs<(add R6, R7, R8, R9, R10)>;
49 def CSR_PreserveAll : CalleeSavedRegs<(add R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10)>;
H A DBPFFrameLowering.cpp35 SavedRegs.reset(BPF::R7); in determineCalleeSaves()
/freebsd/contrib/arm-optimized-routines/math/aarch64/experimental/
H A Derfc_1u8.c34 #define R7 -0x1.8e38e38e38e39p-3 macro
109 double p8 = fma (Q7 * r, p7, p6) * R7; in erfc()
/freebsd/lib/msun/ld128/
H A Ds_atanpil.c70 R7 = -7.38228286468784921885881430313681146e-03L, in __r() local
86 r = R5 + (R6 + (R7 + (R8 + (R9 + R10 * xs) * xs) *xs) * xs) * xs; in __r()
H A Ds_asinpil.c63 R7 = -7.38228286468784921885881430313681146e-03L, in __r() local
79 r = R5 + (R6 + (R7 + (R8 + (R9 + R10 * xs) * xs) *xs) * xs) * xs; in __r()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td43 def R7 : AVRReg<7, "r7">, DwarfRegNum<[7]>;
92 def R7R6 : AVRReg<6, "r7:r6", [R6, R7]>, DwarfRegNum<[6]>;
121 R9, R8, R7, R6, R5, R4, R3, R2, R0, R1)>;
125 (add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6,
/freebsd/sys/contrib/edk2/Include/Protocol/
H A DDebugSupport.h294 UINT64 R7; member
464 UINT64 R7; member
498 UINT32 R7; member
763 UINT64 R7; member
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiBaseInfo.h59 case Lanai::R7: in getLanaiRegisterNumbering()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td59 def R7 : CSKYReg<7, "r7", ["l3"]>, DwarfRegNum<[7]>;
168 // Register class for R0 - R7.
169 // Some 16-bit integer instructions can only access R0 - R7.
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCCallingConv.td32 CCIfType<[i32, i64], CCAssignToReg<[R0, R1, R2, R3, R4, R5, R6, R7]>>,
/freebsd/sys/contrib/device-tree/src/arm/aspeed/
H A Daspeed-bmc-qcom-dc-scm-v1.dts112 /*R0-R7*/ "","","","","","","","",
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMBaseInfo.h164 case R4: case R5: case R6: case R7: in isARMLowRegister()

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