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Searched refs:R600 (Results 1 – 25 of 32) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600RegisterInfo.cpp26 R600::sub0, R600::sub1, R600::sub2, R600::sub3, in getSubRegFromChannel()
27 R600::sub4, R600::sub5, R600::sub6, R600::sub7, in getSubRegFromChannel()
28 R600::sub8, R600::sub9, R600::sub10, R600::sub11, in getSubRegFromChannel()
29 R600::sub12, R600::sub13, R600::sub14, R600::sub15 in getSubRegFromChannel()
42 reserveRegisterTuples(Reserved, R600::ZERO); in getReservedRegs()
43 reserveRegisterTuples(Reserved, R600::HALF); in getReservedRegs()
44 reserveRegisterTuples(Reserved, R600::ONE); in getReservedRegs()
45 reserveRegisterTuples(Reserved, R600::ONE_INT); in getReservedRegs()
46 reserveRegisterTuples(Reserved, R600::NEG_HALF); in getReservedRegs()
47 reserveRegisterTuples(Reserved, R600::NEG_ONE); in getReservedRegs()
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H A DR600InstrInfo.cpp44 if ((R600::R600_Reg128RegClass.contains(DestReg) || in copyPhysReg()
45 R600::R600_Reg128VerticalRegClass.contains(DestReg)) && in copyPhysReg()
46 (R600::R600_Reg128RegClass.contains(SrcReg) || in copyPhysReg()
47 R600::R600_Reg128VerticalRegClass.contains(SrcReg))) { in copyPhysReg()
49 } else if((R600::R600_Reg64RegClass.contains(DestReg) || in copyPhysReg()
50 R600::R600_Reg64VerticalRegClass.contains(DestReg)) && in copyPhysReg()
51 (R600::R600_Reg64RegClass.contains(SrcReg) || in copyPhysReg()
52 R600::R600_Reg64VerticalRegClass.contains(SrcReg))) { in copyPhysReg()
59 buildDefaultInstruction(MBB, MI, R600::MOV, in copyPhysReg()
66 MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, R600::MOV, in copyPhysReg()
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H A DR600ControlFlowFinalizer.cpp67 if (Opcode == R600::CF_ALU_PUSH_BEFORE && ST->hasCaymanISA() && in requiresWorkAroundForInst()
76 case R600::CF_ALU_PUSH_BEFORE: in requiresWorkAroundForInst()
77 case R600::CF_ALU_ELSE_AFTER: in requiresWorkAroundForInst()
78 case R600::CF_ALU_BREAK: in requiresWorkAroundForInst()
79 case R600::CF_ALU_CONTINUE: in requiresWorkAroundForInst()
138 case R600::CF_PUSH_EG: in pushBranch()
139 case R600::CF_ALU_PUSH_BEFORE: in pushBranch()
210 case R600::KILL: in IsTrivialInst()
211 case R600::RETURN: in IsTrivialInst()
223 Opcode = isEg ? R600::CF_TC_EG : R600::CF_TC_R600; in getHWInstrDesc()
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H A DR600ExpandSpecialInstrs.cpp34 R600::OpName Op);
65 R600::OpName Op) { in SetFlagInNewMI()
87 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); in runOnMachineFunction()
91 DstOp.getReg(), R600::OQAP); in runOnMachineFunction()
92 DstOp.setReg(R600::OQAP); in runOnMachineFunction()
94 R600::OpName::pred_sel); in runOnMachineFunction()
96 R600::OpName::pred_sel); in runOnMachineFunction()
105 case R600::PRED_X: { in runOnMachineFunction()
113 R600::ZERO); // src1 in runOnMachineFunction()
116 TII->setImmOperand(*PredSet, R600::OpName::update_exec_mask, 1); in runOnMachineFunction()
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H A DR600EmitClauseMarkers.cpp33 case R600::INTERP_PAIR_XY: in OccupiedDwords()
34 case R600::INTERP_PAIR_ZW: in OccupiedDwords()
35 case R600::INTERP_VEC_LOAD: in OccupiedDwords()
36 case R600::DOT_4: in OccupiedDwords()
38 case R600::KILL: in OccupiedDwords()
58 if (MO.isReg() && MO.getReg() == R600::ALU_LITERAL_X) in OccupiedDwords()
70 case R600::PRED_X: in isALU()
71 case R600::INTERP_PAIR_XY: in isALU()
72 case R600::INTERP_PAIR_ZW: in isALU()
73 case R600::INTERP_VEC_LOAD: in isALU()
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H A DR600ClauseMergePass.cpp28 case R600::CF_ALU: in isCFAlu()
29 case R600::CF_ALU_PUSH_BEFORE: in isCFAlu()
79 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::COUNT)) in getCFAluSize()
86 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::Enabled)) in isCFAluEnabled()
92 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT); in cleanPotentialDisabledCFAlu()
111 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT); in mergeIfPossible()
119 if (RootCFAlu.getOpcode() == R600::CF_ALU_PUSH_BEFORE) in mergeIfPossible()
123 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE0); in mergeIfPossible()
125 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK0); in mergeIfPossible()
127 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_ADDR0); in mergeIfPossible()
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H A DR600MachineScheduler.cpp157 if (MO.isReg() && MO.getReg() == R600::ALU_LITERAL_X) in schedNode()
176 if (MI->getOpcode() != R600::COPY) in isPhysicalRegCopy()
217 case R600::PRED_X: in getAluKind()
219 case R600::INTERP_PAIR_XY: in getAluKind()
220 case R600::INTERP_PAIR_ZW: in getAluKind()
221 case R600::INTERP_VEC_LOAD: in getAluKind()
222 case R600::DOT_4: in getAluKind()
224 case R600::COPY: in getAluKind()
240 MI->getOpcode() == R600::GROUP_BARRIER) { in getAluKind()
251 case R600::sub0: in getAluKind()
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H A DR600Packetizer.cpp81 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::write); in getPreviousVector()
84 int DstIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::dst); in getPreviousVector()
90 Result[Dst] = R600::PS; in getPreviousVector()
93 if (BI->getOpcode() == R600::DOT4_r600 || in getPreviousVector()
94 BI->getOpcode() == R600::DOT4_eg) { in getPreviousVector()
95 Result[Dst] = R600::PV_X; in getPreviousVector()
98 if (Dst == R600::OQAP) { in getPreviousVector()
104 PVReg = R600::PV_X; in getPreviousVector()
107 PVReg = R600::PV_Y; in getPreviousVector()
110 PVReg = R600::PV_Z; in getPreviousVector()
[all …]
H A DR600ISelLowering.cpp32 addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass); in R600TargetLowering()
33 addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass); in R600TargetLowering()
34 addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass); in R600TargetLowering()
35 addRegisterClass(MVT::v2i32, &R600::R600_Reg64RegClass); in R600TargetLowering()
36 addRegisterClass(MVT::v4f32, &R600::R600_Reg128RegClass); in R600TargetLowering()
37 addRegisterClass(MVT::v4i32, &R600::R600_Reg128RegClass); in R600TargetLowering()
212 return std::next(I)->getOpcode() == R600::RETURN; in isEOP()
228 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); in EmitInstrWithCustomInserter()
234 MI.getOpcode() == R600::LDS_CMPST_RET) in EmitInstrWithCustomInserter()
238 TII->get(R600::getLDSNoRetOp(MI.getOpcode()))); in EmitInstrWithCustomInserter()
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H A DR600MachineCFGStructurizer.cpp404 if (I->getOpcode() == R600::PRED_X) { in reversePredicateSetter()
406 case R600::PRED_SETE_INT: in reversePredicateSetter()
407 I->getOperand(2).setImm(R600::PRED_SETNE_INT); in reversePredicateSetter()
409 case R600::PRED_SETNE_INT: in reversePredicateSetter()
410 I->getOperand(2).setImm(R600::PRED_SETE_INT); in reversePredicateSetter()
412 case R600::PRED_SETE: in reversePredicateSetter()
413 I->getOperand(2).setImm(R600::PRED_SETNE); in reversePredicateSetter()
415 case R600::PRED_SETNE: in reversePredicateSetter()
416 I->getOperand(2).setImm(R600::PRED_SETE); in reversePredicateSetter()
485 case R600::JUMP_COND: in getBranchNzeroOpcode()
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H A DR600.td1 //===-- R600.td - R600 Tablegen files ----------------------*- tablegen -*-===//
15 def R600 : Target {
20 let Namespace = "R600" in {
45 // Calling convention for R600
H A DR600ISelDAGToDAG.cpp123 RegClassID = R600::R600_Reg64RegClassID; in Select()
127 RegClassID = R600::R600_Reg128VerticalRegClassID; in Select()
129 RegClassID = R600::R600_Reg128RegClassID; in Select()
148 Base = CurDAG->getRegister(R600::INDIRECT_BASE_ADDR, MVT::i32); in SelectADDRIndirect()
152 Base = CurDAG->getRegister(R600::INDIRECT_BASE_ADDR, MVT::i32); in SelectADDRIndirect()
183 SDLoc(CurDAG->getEntryNode()), R600::ZERO, in SelectADDRVTX_READ()
H A DR600InstrInfo.td1 //===-- R600InstrInfo.td - R600 DAG nodes ------------------*- tablegen -*-===//
9 // This file contains DAG node definitions for the R600 target.
14 // R600 DAG Nodes
H A DR600OptimizeVectorRegisters.cpp56 assert(MI->getOpcode() == R600::REG_SEQUENCE); in RegSeqInfo()
140 case R600::R600_ExportSwz: in canSwizzle()
141 case R600::EG_ExportSwz: in canSwizzle()
190 Register DstReg = MRI->createVirtualRegister(&R600::R600_Reg128RegClass); in RebuildVector()
195 MachineInstr *Tmp = BuildMI(MBB, Pos, DL, TII->get(R600::INSERT_SUBREG), in RebuildVector()
211 BuildMI(MBB, Pos, DL, TII->get(R600::COPY), Reg).addReg(SrcVec); in RebuildVector()
324 if (MI.getOpcode() != R600::REG_SEQUENCE) { in runOnMachineFunction()
H A DR600Processors.td1 //===-- R600Processors.td - R600 Processor definitions --------------------===//
47 def FeatureR600 : R600SubtargetFeatureGeneration<"R600", "r600",
67 // Radeon HD 2000/3000 Series (R600).
H A DR600InstrInfo.h291 int getOperandIdx(const MachineInstr &MI, R600::OpName Op) const;
296 int getOperandIdx(unsigned Opcode, R600::OpName Op) const;
299 void setImmOperand(MachineInstr &MI, R600::OpName Op, int64_t Imm) const;
327 namespace R600 {
H A DR600Schedule.td1 //===-- R600Schedule.td - R600 Scheduling definitions ------*- tablegen -*-===//
9 // R600 has a VLIW architecture. On pre-cayman cards there are 5 instruction
H A DR600InstrFormats.td1 //===-- R600InstrFormats.td - R600 Instruction Encodings ------------------===//
9 // R600 Instruction format definitions.
43 let Namespace = "R600";
189 XXX: R600 subtarget uses a slightly different encoding than the other
H A DR600Instructions.td1 //===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===//
9 // TableGen definitions for instructions which are available on R600 family
16 // FIXME: Should not be arbitrarily split from other R600 inst classes.
20 let Namespace = "R600";
87 usesCustomInserter = 1, Namespace = "R600" in {
365 // R600 SDNodes
368 let Namespace = "R600" in {
431 let Namespace = "R600" in {
674 // Common Instructions R600, R700, Evergreen, Cayman
679 let Namespace = "R600", usesCustomInserte
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H A DR600Subtarget.h40 Generation Gen = R600;
H A DR600AsmPrinter.cpp53 if (MI.getOpcode() == R600::KILLGT) in EmitProgramInfoR600()
H A DAMDGPUSubtarget.h34 R600 = 1, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DR600MCCodeEmitter.cpp90 if (MI.getOpcode() == R600::RETURN || in encodeInstruction()
91 MI.getOpcode() == R600::FETCH_CLAUSE || in encodeInstruction()
92 MI.getOpcode() == R600::ALU_CLAUSE || in encodeInstruction()
93 MI.getOpcode() == R600::BUNDLE || in encodeInstruction()
94 MI.getOpcode() == R600::KILL) { in encodeInstruction()
100 if (!(STI.hasFeature(R600::FeatureCaymanISA))) { in encodeInstruction()
128 if ((STI.hasFeature(R600::FeatureR600ALUInst)) && in encodeInstruction()
H A DR600InstPrinter.cpp147 case R600::PRED_SEL_OFF: in printOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/TargetInfo/
H A DAMDGPUTargetInfo.cpp34 RegisterTarget<Triple::r600, false> R600(getTheR600Target(), "r600", in LLVMInitializeAMDGPUTargetInfo() local

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