Lines Matching refs:R600
45 if ((R600::R600_Reg128RegClass.contains(DestReg) || in copyPhysReg()
46 R600::R600_Reg128VerticalRegClass.contains(DestReg)) && in copyPhysReg()
47 (R600::R600_Reg128RegClass.contains(SrcReg) || in copyPhysReg()
48 R600::R600_Reg128VerticalRegClass.contains(SrcReg))) { in copyPhysReg()
50 } else if((R600::R600_Reg64RegClass.contains(DestReg) || in copyPhysReg()
51 R600::R600_Reg64VerticalRegClass.contains(DestReg)) && in copyPhysReg()
52 (R600::R600_Reg64RegClass.contains(SrcReg) || in copyPhysReg()
53 R600::R600_Reg64VerticalRegClass.contains(SrcReg))) { in copyPhysReg()
60 buildDefaultInstruction(MBB, MI, R600::MOV, in copyPhysReg()
67 MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, R600::MOV, in copyPhysReg()
69 NewMI->getOperand(getOperandIdx(*NewMI, R600::OpName::src0)) in copyPhysReg()
90 case R600::MOV: in isMov()
91 case R600::MOV_IMM_F32: in isMov()
92 case R600::MOV_IMM_I32: in isMov()
104 case R600::CUBE_r600_pseudo: in isCubeOp()
105 case R600::CUBE_r600_real: in isCubeOp()
106 case R600::CUBE_eg_pseudo: in isCubeOp()
107 case R600::CUBE_eg_real: in isCubeOp()
135 return isLDSInstr(Opcode) && getOperandIdx(Opcode, R600::OpName::dst) != -1; in isLDSRetInstr()
144 case R600::PRED_X: in canBeConsideredALU()
145 case R600::INTERP_PAIR_XY: in canBeConsideredALU()
146 case R600::INTERP_PAIR_ZW: in canBeConsideredALU()
147 case R600::INTERP_VEC_LOAD: in canBeConsideredALU()
148 case R600::COPY: in canBeConsideredALU()
149 case R600::DOT_4: in canBeConsideredALU()
159 return (get(Opcode).getSchedClass() == R600::Sched::TransALU); in isTransOnly()
167 return (get(Opcode).getSchedClass() == R600::Sched::VecALU); in isVectorOnly()
201 case R600::KILLGT: in mustBeLastInClause()
202 case R600::GROUP_BARRIER: in mustBeLastInClause()
210 return MI.findRegisterUseOperandIdx(R600::AR_X, &RI, false) != -1; in usesAddressRegister()
214 return MI.findRegisterDefOperandIdx(R600::AR_X, &RI, false, false) != -1; in definesAddressRegister()
227 if (R600::R600_LDS_SRC_REGRegClass.contains(I->getReg())) in readsLDSSrcReg()
235 {R600::OpName::src0, R600::OpName::src0_sel}, in getSelIdx()
236 {R600::OpName::src1, R600::OpName::src1_sel}, in getSelIdx()
237 {R600::OpName::src2, R600::OpName::src2_sel}, in getSelIdx()
238 {R600::OpName::src0_X, R600::OpName::src0_sel_X}, in getSelIdx()
239 {R600::OpName::src0_Y, R600::OpName::src0_sel_Y}, in getSelIdx()
240 {R600::OpName::src0_Z, R600::OpName::src0_sel_Z}, in getSelIdx()
241 {R600::OpName::src0_W, R600::OpName::src0_sel_W}, in getSelIdx()
242 {R600::OpName::src1_X, R600::OpName::src1_sel_X}, in getSelIdx()
243 {R600::OpName::src1_Y, R600::OpName::src1_sel_Y}, in getSelIdx()
244 {R600::OpName::src1_Z, R600::OpName::src1_sel_Z}, in getSelIdx()
245 {R600::OpName::src1_W, R600::OpName::src1_sel_W} in getSelIdx()
260 if (MI.getOpcode() == R600::DOT_4) { in getSrcs()
262 {R600::OpName::src0_X, R600::OpName::src0_sel_X}, in getSrcs()
263 {R600::OpName::src0_Y, R600::OpName::src0_sel_Y}, in getSrcs()
264 {R600::OpName::src0_Z, R600::OpName::src0_sel_Z}, in getSrcs()
265 {R600::OpName::src0_W, R600::OpName::src0_sel_W}, in getSrcs()
266 {R600::OpName::src1_X, R600::OpName::src1_sel_X}, in getSrcs()
267 {R600::OpName::src1_Y, R600::OpName::src1_sel_Y}, in getSrcs()
268 {R600::OpName::src1_Z, R600::OpName::src1_sel_Z}, in getSrcs()
269 {R600::OpName::src1_W, R600::OpName::src1_sel_W}, in getSrcs()
275 if (Reg == R600::ALU_CONST) { in getSrcs()
286 {R600::OpName::src0, R600::OpName::src0_sel}, in getSrcs()
287 {R600::OpName::src1, R600::OpName::src1_sel}, in getSrcs()
288 {R600::OpName::src2, R600::OpName::src2_sel}, in getSrcs()
297 if (Reg == R600::ALU_CONST) { in getSrcs()
302 if (Reg == R600::ALU_LITERAL_X) { in getSrcs()
304 MI.getOperand(getOperandIdx(MI.getOpcode(), R600::OpName::literal)); in getSrcs()
328 if (Reg == R600::OQAP) { in ExtractSrcs()
419 if (Src.first == GET_REG_INDEX(RI.getEncodingValue(R600::OQAP))) { in isLegalUpTo()
524 unsigned Op = getOperandIdx(MI->getOpcode(), R600::OpName::bank_swizzle); in fitsReadPortLimitations()
591 if (Src.first->getReg() == R600::ALU_LITERAL_X) in fitsConstReadLimitations()
595 if (Src.first->getReg() == R600::ALU_CONST) in fitsConstReadLimitations()
597 if (R600::R600_KC0RegClass.contains(Src.first->getReg()) || in fitsConstReadLimitations()
598 R600::R600_KC1RegClass.contains(Src.first->getReg())) { in fitsConstReadLimitations()
617 case R600::PRED_X: in isPredicateSetter()
639 return Opcode == R600::JUMP || Opcode == R600::JUMP_COND; in isJump()
643 return Opcode == R600::BRANCH || Opcode == R600::BRANCH_COND_i32 || in isBranch()
644 Opcode == R600::BRANCH_COND_f32; in isBranch()
668 while (I != MBB.begin() && std::prev(I)->getOpcode() == R600::JUMP) { in analyzeBranch()
679 if (LastOpc == R600::JUMP) { in analyzeBranch()
683 if (LastOpc == R600::JUMP_COND) { in analyzeBranch()
691 Cond.push_back(MachineOperand::CreateReg(R600::PRED_SEL_ONE, false)); in analyzeBranch()
702 if (SecondLastOpc == R600::JUMP_COND && LastOpc == R600::JUMP) { in analyzeBranch()
711 Cond.push_back(MachineOperand::CreateReg(R600::PRED_SEL_ONE, false)); in analyzeBranch()
723 if (It->getOpcode() == R600::CF_ALU || in FindLastAluClause()
724 It->getOpcode() == R600::CF_ALU_PUSH_BEFORE) in FindLastAluClause()
741 BuildMI(&MBB, DL, get(R600::JUMP)).addMBB(TBB); in insertBranch()
749 BuildMI(&MBB, DL, get(R600::JUMP_COND)) in insertBranch()
751 .addReg(R600::PREDICATE_BIT, RegState::Kill); in insertBranch()
755 assert (CfAlu->getOpcode() == R600::CF_ALU); in insertBranch()
756 CfAlu->setDesc(get(R600::CF_ALU_PUSH_BEFORE)); in insertBranch()
763 BuildMI(&MBB, DL, get(R600::JUMP_COND)) in insertBranch()
765 .addReg(R600::PREDICATE_BIT, RegState::Kill); in insertBranch()
766 BuildMI(&MBB, DL, get(R600::JUMP)).addMBB(FBB); in insertBranch()
770 assert(CfAlu->getOpcode() == R600::CF_ALU); in insertBranch()
771 CfAlu->setDesc(get(R600::CF_ALU_PUSH_BEFORE)); in insertBranch()
791 case R600::JUMP_COND: { in removeBranch()
798 assert (CfAlu->getOpcode() == R600::CF_ALU_PUSH_BEFORE); in removeBranch()
799 CfAlu->setDesc(get(R600::CF_ALU)); in removeBranch()
802 case R600::JUMP: in removeBranch()
816 case R600::JUMP_COND: { in removeBranch()
823 assert (CfAlu->getOpcode() == R600::CF_ALU_PUSH_BEFORE); in removeBranch()
824 CfAlu->setDesc(get(R600::CF_ALU)); in removeBranch()
827 case R600::JUMP: in removeBranch()
842 case R600::PRED_SEL_ONE: in isPredicated()
843 case R600::PRED_SEL_ZERO: in isPredicated()
844 case R600::PREDICATE_BIT: in isPredicated()
855 if (MI.getOpcode() == R600::KILLGT) in isPredicable()
857 if (MI.getOpcode() == R600::CF_ALU) { in isPredicable()
907 case R600::PRED_SETE_INT: in reverseBranchCondition()
908 MO.setImm(R600::PRED_SETNE_INT); in reverseBranchCondition()
910 case R600::PRED_SETNE_INT: in reverseBranchCondition()
911 MO.setImm(R600::PRED_SETE_INT); in reverseBranchCondition()
913 case R600::PRED_SETE: in reverseBranchCondition()
914 MO.setImm(R600::PRED_SETNE); in reverseBranchCondition()
916 case R600::PRED_SETNE: in reverseBranchCondition()
917 MO.setImm(R600::PRED_SETE); in reverseBranchCondition()
925 case R600::PRED_SEL_ZERO: in reverseBranchCondition()
926 MO2.setReg(R600::PRED_SEL_ONE); in reverseBranchCondition()
928 case R600::PRED_SEL_ONE: in reverseBranchCondition()
929 MO2.setReg(R600::PRED_SEL_ZERO); in reverseBranchCondition()
947 if (MI.getOpcode() == R600::CF_ALU) { in PredicateInstruction()
952 if (MI.getOpcode() == R600::DOT_4) { in PredicateInstruction()
953 MI.getOperand(getOperandIdx(MI, R600::OpName::pred_sel_X)) in PredicateInstruction()
955 MI.getOperand(getOperandIdx(MI, R600::OpName::pred_sel_Y)) in PredicateInstruction()
957 MI.getOperand(getOperandIdx(MI, R600::OpName::pred_sel_Z)) in PredicateInstruction()
959 MI.getOperand(getOperandIdx(MI, R600::OpName::pred_sel_W)) in PredicateInstruction()
962 MIB.addReg(R600::PREDICATE_BIT, RegState::Implicit); in PredicateInstruction()
970 MIB.addReg(R600::PREDICATE_BIT, RegState::Implicit); in PredicateInstruction()
1000 R600::getNamedOperandIdx(MI.getOpcode(), R600::OpName::addr); in expandPostRAPseudo()
1005 R600::getNamedOperandIdx(MI.getOpcode(), R600::OpName::chan); in expandPostRAPseudo()
1008 R600::getNamedOperandIdx(MI.getOpcode(), R600::OpName::dst); in expandPostRAPseudo()
1013 if (OffsetReg == R600::INDIRECT_BASE_ADDR) { in expandPostRAPseudo()
1022 R600::getNamedOperandIdx(MI.getOpcode(), R600::OpName::val); in expandPostRAPseudo()
1027 if (OffsetReg == R600::INDIRECT_BASE_ADDR) { in expandPostRAPseudo()
1042 case R600::R600_EXTRACT_ELT_V2: in expandPostRAPseudo()
1043 case R600::R600_EXTRACT_ELT_V4: in expandPostRAPseudo()
1049 case R600::R600_INSERT_ELT_V2: in expandPostRAPseudo()
1050 case R600::R600_INSERT_ELT_V4: in expandPostRAPseudo()
1075 unsigned Reg = R600::R600_TReg32RegClass.getRegister((4 * Index) + Chan); in reserveIndirectRegisters()
1082 return &R600::R600_TReg32_XRegClass; in getIndirectAddrRegClass()
1100 case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break; in buildIndirectWrite()
1101 case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(Address); break; in buildIndirectWrite()
1102 case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(Address); break; in buildIndirectWrite()
1103 case 3: AddrReg = R600::R600_Addr_WRegClass.getRegister(Address); break; in buildIndirectWrite()
1105 MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, R600::MOVA_INT_eg, in buildIndirectWrite()
1106 R600::AR_X, OffsetReg); in buildIndirectWrite()
1107 setImmOperand(*MOVA, R600::OpName::write, 0); in buildIndirectWrite()
1109 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, R600::MOV, in buildIndirectWrite()
1111 .addReg(R600::AR_X, in buildIndirectWrite()
1113 setImmOperand(*Mov, R600::OpName::dst_rel, 1); in buildIndirectWrite()
1132 case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break; in buildIndirectRead()
1133 case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(Address); break; in buildIndirectRead()
1134 case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(Address); break; in buildIndirectRead()
1135 case 3: AddrReg = R600::R600_Addr_WRegClass.getRegister(Address); break; in buildIndirectRead()
1137 MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, R600::MOVA_INT_eg, in buildIndirectRead()
1138 R600::AR_X, in buildIndirectRead()
1140 setImmOperand(*MOVA, R600::OpName::write, 0); in buildIndirectRead()
1141 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, R600::MOV, in buildIndirectRead()
1144 .addReg(R600::AR_X, in buildIndirectRead()
1146 setImmOperand(*Mov, R600::OpName::src0_rel, 1); in buildIndirectRead()
1243 .addReg(R600::PRED_SEL_OFF) // $pred_sel in buildDefaultInstruction()
1264 OPERAND_CASE(R600::OpName::update_exec_mask) in getSlotedOps()
1265 OPERAND_CASE(R600::OpName::update_pred) in getSlotedOps()
1266 OPERAND_CASE(R600::OpName::write) in getSlotedOps()
1267 OPERAND_CASE(R600::OpName::omod) in getSlotedOps()
1268 OPERAND_CASE(R600::OpName::dst_rel) in getSlotedOps()
1269 OPERAND_CASE(R600::OpName::clamp) in getSlotedOps()
1270 OPERAND_CASE(R600::OpName::src0) in getSlotedOps()
1271 OPERAND_CASE(R600::OpName::src0_neg) in getSlotedOps()
1272 OPERAND_CASE(R600::OpName::src0_rel) in getSlotedOps()
1273 OPERAND_CASE(R600::OpName::src0_abs) in getSlotedOps()
1274 OPERAND_CASE(R600::OpName::src0_sel) in getSlotedOps()
1275 OPERAND_CASE(R600::OpName::src1) in getSlotedOps()
1276 OPERAND_CASE(R600::OpName::src1_neg) in getSlotedOps()
1277 OPERAND_CASE(R600::OpName::src1_rel) in getSlotedOps()
1278 OPERAND_CASE(R600::OpName::src1_abs) in getSlotedOps()
1279 OPERAND_CASE(R600::OpName::src1_sel) in getSlotedOps()
1280 OPERAND_CASE(R600::OpName::pred_sel) in getSlotedOps()
1291 assert (MI->getOpcode() == R600::DOT_4 && "Not Implemented"); in buildSlotOfVectorInstruction()
1294 Opcode = R600::DOT4_r600; in buildSlotOfVectorInstruction()
1296 Opcode = R600::DOT4_eg; in buildSlotOfVectorInstruction()
1299 getOperandIdx(MI->getOpcode(), getSlotedOps(R600::OpName::src0, Slot))); in buildSlotOfVectorInstruction()
1301 getOperandIdx(MI->getOpcode(), getSlotedOps(R600::OpName::src1, Slot))); in buildSlotOfVectorInstruction()
1305 R600::OpName::update_exec_mask, in buildSlotOfVectorInstruction()
1306 R600::OpName::update_pred, in buildSlotOfVectorInstruction()
1307 R600::OpName::write, in buildSlotOfVectorInstruction()
1308 R600::OpName::omod, in buildSlotOfVectorInstruction()
1309 R600::OpName::dst_rel, in buildSlotOfVectorInstruction()
1310 R600::OpName::clamp, in buildSlotOfVectorInstruction()
1311 R600::OpName::src0_neg, in buildSlotOfVectorInstruction()
1312 R600::OpName::src0_rel, in buildSlotOfVectorInstruction()
1313 R600::OpName::src0_abs, in buildSlotOfVectorInstruction()
1314 R600::OpName::src0_sel, in buildSlotOfVectorInstruction()
1315 R600::OpName::src1_neg, in buildSlotOfVectorInstruction()
1316 R600::OpName::src1_rel, in buildSlotOfVectorInstruction()
1317 R600::OpName::src1_abs, in buildSlotOfVectorInstruction()
1318 R600::OpName::src1_sel, in buildSlotOfVectorInstruction()
1322 getSlotedOps(R600::OpName::pred_sel, Slot))); in buildSlotOfVectorInstruction()
1323 MIB->getOperand(getOperandIdx(Opcode, R600::OpName::pred_sel)) in buildSlotOfVectorInstruction()
1340 MachineInstr *MovImm = buildDefaultInstruction(BB, I, R600::MOV, DstReg, in buildMovImm()
1341 R600::ALU_LITERAL_X); in buildMovImm()
1342 setImmOperand(*MovImm, R600::OpName::literal, Imm); in buildMovImm()
1349 return buildDefaultInstruction(*MBB, I, R600::MOV, DstReg, SrcReg); in buildMovInstr()
1357 return R600::getNamedOperandIdx(Opcode, Op); in getOperandIdx()
1384 FlagIndex = getOperandIdx(MI, R600::OpName::clamp); in getFlagOp()
1387 FlagIndex = getOperandIdx(MI, R600::OpName::write); in getFlagOp()
1391 FlagIndex = getOperandIdx(MI, R600::OpName::last); in getFlagOp()
1396 FlagIndex = getOperandIdx(MI, R600::OpName::src0_neg); in getFlagOp()
1399 FlagIndex = getOperandIdx(MI, R600::OpName::src1_neg); in getFlagOp()
1402 FlagIndex = getOperandIdx(MI, R600::OpName::src2_neg); in getFlagOp()
1413 FlagIndex = getOperandIdx(MI, R600::OpName::src0_abs); in getFlagOp()
1416 FlagIndex = getOperandIdx(MI, R600::OpName::src1_abs); in getFlagOp()