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Searched refs:R10 (Results 1 – 25 of 70) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallingConv.td27 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
53 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
122 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
172 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
190 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
217 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
240 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
270 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
275 def CSR_Win_AAPCS_CFGuard_Check : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7,
281 // R10 is used to pass swiftself, remove it from CSR.
[all …]
H A DARMBaseRegisterInfo.h54 case R8: case R9: case R10: case R11: case R12: in isARMArea1Register()
66 case R8: case R9: case R10: case R11: case R12: in isARMArea2Register()
81 case R8: case R9: case R10: case R12: in isSplitFPArea1Register()
H A DARMSLSHardening.cpp144 {"__llvm_slsblr_thunk_arm_r10", ARM::R10, false},
158 {"__llvm_slsblr_thunk_thumb_r10", ARM::R10, true},
H A DThumb1FrameLowering.cpp223 case ARM::R10: in emitPrologue()
365 case ARM::R10: in emitPrologue()
399 case ARM::R10: in emitPrologue()
835 ARM::R10, ARM::R11};
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.cpp43 MSP430::R8, MSP430::R9, MSP430::R10, in getCalleeSavedRegs()
48 MSP430::R8, MSP430::R9, MSP430::R10, in getCalleeSavedRegs()
53 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
59 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
H A DMSP430RegisterInfo.td65 def R10 : MSP430RegWithSubregs<10, "r10", [R10B]>, DwarfRegNum<[10]>;
83 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.td35 def R10 : Ri<10, "r10">, DwarfRegNum<[10]>;
48 R4, R5, R6, R7, R8, R9, R10,
55 R4, R5, R6, R7, R8, R9, R10,
H A DXCoreRegisterInfo.cpp218 XCore::R8, XCore::R9, XCore::R10, in getCalleeSavedRegs()
241 Reserved.set(XCore::R10); in getReservedRegs()
326 return TFI->hasFP(MF) ? XCore::R10 : XCore::SP; in getFrameRegister()
H A DXCoreFrameLowering.cpp34 static const unsigned FramePtr = XCore::R10;
431 assert(Reg != XCore::LR && !(Reg == XCore::R10 && hasFP(*MF)) && in spillCalleeSavedRegisters()
459 assert(Reg != XCore::LR && !(Reg == XCore::R10 && hasFP(*MF)) && in restoreCalleeSavedRegisters()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td35 def RR1 : LanaiReg<10, "rr1", [R10]>, DwarfRegAlias<R10>;
50 R10, RR1, R11, RR2, // programmer controlled registers
H A DLanaiRegisterInfo.cpp54 Reserved.set(Lanai::R10); in getReservedRegs()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.cpp74 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_AlignArgRegs()
99 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
151 static const MCPhysReg LoRegList[] = { PPC::R4, PPC::R6, PPC::R8, PPC::R10 }; in CC_PPC32_SPE_CustomSplitFP64()
H A DPPCCallingConv.td78 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
89 CCIfType<[f32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>,
223 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
238 CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>,
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td46 def R10 : AVRReg<10, "r10">, DwarfRegNum<[10]>;
90 def R11R10 : AVRReg<10, "r11:r10", [R10, R11]>, DwarfRegNum<[10]>;
106 def R10R9 : AVRReg<9, "r10:r9", [R9, R10]>, DwarfRegNum<[9]>;
121 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
126 (add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6,
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiBaseInfo.h66 case Lanai::R10: in getLanaiRegisterNumbering()
/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/hexagon/
H A Dfastmath2_dlib_asm.S71 #define minminl R10
172 #define minminl R10
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFRegisterInfo.td50 R10 // Frame Ptr
H A DBPFCallingConv.td48 def CSR : CalleeSavedRegs<(add R6, R7, R8, R9, R10)>;
H A DBPFRegisterInfo.cpp135 return BPF::R10; in getFrameRegister()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallingConv.td90 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15];
95 // Change in __regcall ABI v.4: additionally don't use R10 as a
540 // The 'nest' parameter, if any, is passed in R10.
542 CCIfNest<CCAssignToReg<[R10]>>,
641 // The 'nest' parameter, if any, is passed in R10.
642 CCIfNest<CCAssignToReg<[R10]>>,
1063 // - R10 'nest' parameter
1162 R8, R9, R10, R11)>;
1172 R8, R9, R10)>;
1183 def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
[all …]
H A DX86RegisterInfo.td293 def R10 : X86Reg<"r10", 10, [R10D]>, DwarfRegNum<[10, -2, -2]>;
586 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, R16, R17,
590 // GR64PLTSafe - 64-bit GPRs without R10, R11, RSP and RIP. Could be used when
598 def GR64_ArgRef: RegisterClass<"X86", [i64], 64, (add R10, R11)> {
634 R8, R9, R10, R11,
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/Disassembler/
H A DBPFDisassembler.cpp98 BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, BPF::R11};
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h298 ENTRY(R10) \
332 ENTRY(R10) \
/freebsd/sys/amd64/amd64/
H A Dbpf_jit_machdep.h50 #define R10 2 macro
/freebsd/contrib/llvm-project/libunwind/src/
H A DUnwindCursor.hpp598 _msContext.R10 = r.getRegister(UNW_X86_64_R10); in UnwindCursor()
652 _msContext.R10 = r.getRegister(UNW_ARM_R10); in UnwindCursor()
722 case UNW_X86_64_R10: return _msContext.R10; in getReg()
739 case UNW_ARM_R10: return _msContext.R10; in getReg()
773 case UNW_X86_64_R10: _msContext.R10 = value; break; in setReg()
790 case UNW_ARM_R10: _msContext.R10 = value; break; in setReg()

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