| /freebsd/lib/msun/src/ |
| H A D | s_expm1.c | 124 Q5 = -2.01099218183624371326e-07; /* BE8AFDB7 6E09C32D */ variable
182 r1 = one+hxs*(Q1+hxs*(Q2+hxs*(Q3+hxs*(Q4+hxs*Q5)))); in expm1()
|
| /freebsd/contrib/arm-optimized-routines/pl/math/ |
| H A D | erfc_1u8.c | 25 #define Q5 0x1.3333333333333p0 macro
107 double p6 = fma (Q5 * r, p5, p4) * R5; in erfc()
|
| /freebsd/crypto/openssl/test/recipes/20-test_dhparam_check_data/valid/ |
| H A D | dhx_ffdhe2048.pem | 9 ae+Paur+srCSGfqPr4M3aEKxsqqe9o152quJrz+r5JrMJ4Y4cHNFu/FTRO159/Q5
|
| /freebsd/lib/msun/bsdsrc/ |
| H A D | b_tgamma.c | 174 Q5 = 5.1244934798066622e-3, variable
185 q = Q0 + z * (Q1 + z * (Q2 + z * (Q3 + z * (Q4 + z * (Q5 + in ratfun_gam()
|
| /freebsd/lib/msun/ld80/ |
| H A D | b_tgammal.c | 197 #define Q5 (Q5u.e) macro
208 q = 1 + z * (Q1 + z * (Q2 + z * (Q3 + z * (Q4 + z * (Q5 + in ratfun_gam()
|
| /freebsd/sys/contrib/device-tree/src/arm/allwinner/ |
| H A D | sun4i-a10-jesurun-q5.dts | 52 model = "Jesurun Q5";
|
| H A D | sun7i-a20-i12-tvbox.dts | 51 model = "I12 / Q5 / QT840A A20 tvbox";
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64CallingConvention.cpp | 36 AArch64::Q3, AArch64::Q4, AArch64::Q5,
|
| H A D | AArch64PBQPRegAlloc.cpp | 74 case AArch64::Q5: in isOdd()
|
| H A D | AArch64CallingConvention.td | 108 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
154 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
397 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
491 CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>,
|
| H A D | AArch64RegisterInfo.td | 423 def Q5 : AArch64Reg<5, "q5", [D5], ["v5", ""]>, DwarfRegAlias<B5>;
863 def Z5 : AArch64Reg<5, "z5", [Q5]>, DwarfRegNum<[101]>;
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/Disassembler/ |
| H A D | SparcDisassembler.cpp | 96 SP::Q5, SP::Q13, ~0U, ~0U,
|
| /freebsd/sys/contrib/device-tree/src/arm/aspeed/ |
| H A D | aspeed-bmc-tyan-s8036.dts | 447 /*Q5*/ "",
|
| H A D | aspeed-bmc-tyan-s7106.dts | 507 /*Q5*/ "BMC_PE_SMB_SW_BIT1", /* out */
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.cpp | 317 {codeview::RegisterId::ARM_NQ5, ARM::Q5}, in initLLVMToCVRegMapping()
|
| H A D | ARMMCCodeEmitter.cpp | 562 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7: in getMachineOpValue()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcRegisterInfo.td | 286 def Q5 : Rq<20, "f20", [D10, D11]>;
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMCallingConv.td | 114 CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>,
|
| H A D | ARMRegisterInfo.td | 164 def Q5 : ARMReg< 5, "q5", [D10, D11]>;
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 210 {codeview::RegisterId::ARM64_Q5, AArch64::Q5}, in initLLVMToCVRegMapping()
|
| H A D | AArch64InstPrinter.cpp | 1516 case AArch64::Q4: Reg = AArch64::Q5; break; in getNextVectorRegister()
1517 case AArch64::Q5: Reg = AArch64::Q6; break; in getNextVectorRegister()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/Disassembler/ |
| H A D | VEDisassembler.cpp | 93 VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q4, VE::Q5, VE::Q6, VE::Q7,
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/ |
| H A D | VEAsmParser.cpp | 126 VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q4, VE::Q5, VE::Q6, VE::Q7,
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 181 Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1573 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1592 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
|