| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64CallLowering.cpp | 61 static void applyStackPassedSmallTypeDAGHack(EVT OrigVT, MVT &ValVT, in applyStackPassedSmallTypeDAGHack() argument
69 if (OrigVT == MVT::i1 || OrigVT == MVT::i8) in applyStackPassedSmallTypeDAGHack()
71 else if (OrigVT == MVT::i16) in applyStackPassedSmallTypeDAGHack()
90 bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT, in assignArg()
94 applyStackPassedSmallTypeDAGHack(OrigVT, ValVT, LocVT); in assignArg()
95 return IncomingValueAssigner::assignArg(ValNo, OrigVT, ValVT, LocVT, in assignArg()
116 bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT, in assignArg()
128 applyStackPassedSmallTypeDAGHack(OrigVT, ValVT, LocVT); in assignArg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsCallLowering.cpp | 41 bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT, in assignArg()
53 ValNo, OrigVT, ValVT, LocVT, LocInfo, Info, Flags, State); in assignArg()
69 bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT, in assignArg()
81 ValNo, OrigVT, ValVT, LocVT, LocInfo, Info, Flags, State); in assignArg()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 2684 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { in AddPromotedToType() argument
2685 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; in AddPromotedToType()
2690 void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { in setOperationPromotedToType() argument
2691 setOperationAction(Opc, OrigVT, Promote); in setOperationPromotedToType()
2692 AddPromotedToType(Opc, OrigVT, DestVT); in setOperationPromotedToType()
2694 void setOperationPromotedToType(ArrayRef<unsigned> Ops, MVT OrigVT, in setOperationPromotedToType() argument
2697 setOperationAction(Op, OrigVT, Promote); in setOperationPromotedToType()
2698 AddPromotedToType(Op, OrigVT, DestVT); in setOperationPromotedToType()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVCallLowering.cpp | 47 bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT, in assignArg()
193 bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT, in assignArg()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CallLowering.h | 199 virtual bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT, in assignArg()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CallLowering.cpp | 787 const EVT OrigVT = EVT::getEVT(Args[i].Ty); in handleAssignments() local
831 bool BigEndianPartOrdering = TLI->hasBigEndianPartOrdering(OrigVT, DL); in handleAssignments()
974 if (Handler.isIncomingArgumentHandler() && OrigVT != LocVT && in handleAssignments()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | |
| H A D | X86ISelLowering.cpp | 32149 MVT OrigVT = VT; in LowerMGATHER() local
32176 SDValue Extract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OrigVT, in LowerMGATHER()
52839 EVT OrigVT = N->getValueType(0); in combineFneg() local
52861 return DAG.getBitcast(OrigVT, NewNode); in combineFneg()
52868 return DAG.getBitcast(OrigVT, NegArg); in combineFneg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86CallLowering.cpp | 69 bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT, in assignArg()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 330 EVT OrigVT = VT; in ExpandConstantFP() local
341 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) && in ExpandConstantFP()
342 TLI.ShouldShrinkFPConstant(OrigVT)) { in ExpandConstantFP()
357 ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx, in ExpandConstantFP()
363 OrigVT, dl, DAG.getEntryNode(), CPIdx, in ExpandConstantFP()
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| H A D | LegalizeVectorTypes.cpp | 7174 EVT OrigVT = N->getOperand(0).getValueType(); in WidenVecOp_VECREDUCE()
7176 EVT ElemVT = OrigVT.getVectorElementType(); in WidenVecOp_VECREDUCE()
7185 unsigned OrigElts = OrigVT.getVectorMinNumElements(); in WidenVecOp_VECREDUCE()
7212 EVT OrigVT = VecOp.getValueType(); in WidenVecOp_VECREDUCE_SEQ()
7214 EVT ElemVT = OrigVT.getVectorElementType(); in WidenVecOp_VECREDUCE_SEQ()
7222 unsigned OrigElts = OrigVT.getVectorMinNumElements(); in WidenVecOp_VECREDUCE_SEQ()
7170 EVT OrigVT = N->getOperand(0).getValueType(); WidenVecOp_VECREDUCE() local
7208 EVT OrigVT = VecOp.getValueType(); WidenVecOp_VECREDUCE_SEQ() local
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| H A D | DAGCombiner.cpp | 13134 EVT OrigVT = N->getOperand(0).getValueType(); in CombineZExtLogicopShiftLoad() local
13135 if (TLI.isZExtFree(OrigVT, VT)) in CombineZExtLogicopShiftLoad()
13390 EVT OrigVT = ALoad->getValueType(0); in tryToFoldExtOfAtomicLoad() local
13391 assert(OrigVT.getSizeInBits() < VT.getSizeInBits() && "VT should be wider."); in tryToFoldExtOfAtomicLoad()
13398 DAG.getNode(ISD::TRUNCATE, SDLoc(ALoad), OrigVT, SDValue(NewALoad, 0))); in tryToFoldExtOfAtomicLoad()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 5630 EVT OrigVT = Op.getOperand(0).getValueType(); in IsMulWideOperandDemotable() local
5631 if (OrigVT.getFixedSizeInBits() <= OptSize) { in IsMulWideOperandDemotable()
5636 EVT OrigVT = Op.getOperand(0).getValueType(); in IsMulWideOperandDemotable() local
5637 if (OrigVT.getFixedSizeInBits() <= OptSize) { in IsMulWideOperandDemotable()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 4118 static Align CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT, in CalculateStackSlotAlignment() argument
4147 if (Flags.isSplit() && OrigVT != MVT::ppcf128) in CalculateStackSlotAlignment()
4148 Alignment = Align(OrigVT.getStoreSize()); in CalculateStackSlotAlignment()
4160 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT, ISD::ArgFlagsTy Flags, in CalculateStackSlotUsed() argument
4169 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize); in CalculateStackSlotUsed()
4562 EVT OrigVT = Ins[ArgNo].ArgVT; in LowerFormalArguments_64SVR4() local
4578 CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize); in LowerFormalArguments_64SVR4()
6309 EVT OrigVT = Outs[i].ArgVT; in LowerCall_64SVR4() local
6354 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize); in LowerCall_64SVR4()
6423 EVT OrigVT = Outs[i].ArgVT; in LowerCall_64SVR4() local
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 9488 static EVT getExtensionTo64Bits(const EVT &OrigVT) { in getExtensionTo64Bits() argument
9489 if (OrigVT.getSizeInBits() >= 64) in getExtensionTo64Bits()
9490 return OrigVT; in getExtensionTo64Bits()
9492 assert(OrigVT.isSimple() && "Expecting a simple value type"); in getExtensionTo64Bits()
9494 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy; in getExtensionTo64Bits()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 4949 static EVT getExtensionTo64Bits(const EVT &OrigVT) { in getExtensionTo64Bits() argument
4950 if (OrigVT.getSizeInBits() >= 64) in getExtensionTo64Bits()
4951 return OrigVT; in getExtensionTo64Bits()
4953 assert(OrigVT.isSimple() && "Expecting a simple value type"); in getExtensionTo64Bits()
4955 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy; in getExtensionTo64Bits()
|