/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | GCNDPPCombine.cpp | 63 MachineInstr *createDPPInst(MachineInstr &OrigMI, MachineInstr &MovMI, 68 MachineInstr *createDPPInst(MachineInstr &OrigMI, MachineInstr &MovMI, 205 MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI, in createDPPInst() argument 215 auto OrigOp = OrigMI.getOpcode(); in createDPPInst() 235 auto DPPInst = BuildMI(*OrigMI.getParent(), OrigMI, in createDPPInst() 236 OrigMI.getDebugLoc(), TII->get(DPPOp)) in createDPPInst() 237 .setMIFlags(OrigMI.getFlags()); in createDPPInst() 242 if (auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst)) { in createDPPInst() 246 if (auto *SDst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::sdst)) { in createDPPInst() 278 auto *Mod0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0_modifiers); in createDPPInst() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | LiveRangeEdit.cpp | 106 bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI, in allUsesAvailableAt() argument 111 for (const MachineOperand &MO : OrigMI->operands()) { in allUsesAvailableAt() 168 assert(RM.OrigMI && "No defining instruction for remattable value"); in canRematerializeAt() 169 DefIdx = LIS.getInstructionIndex(*RM.OrigMI); in canRematerializeAt() 172 if (cheapAsAMove && !TII.isAsCheapAsAMove(*RM.OrigMI)) in canRematerializeAt() 176 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx)) in canRematerializeAt() 188 assert(RM.OrigMI && "Invalid remat"); in rematerializeAt() 189 TII.reMaterialize(MBB, MI, DestReg, SubIdx, *RM.OrigMI, tri); in rematerializeAt()
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H A D | ModuloSchedule.cpp | 1165 MachineInstr *OrigMI = OrigInstr->second; in rewriteScheduledInstr() local 1166 int StageSched = Schedule.getStage(OrigMI); in rewriteScheduledInstr() 1167 int CycleSched = Schedule.getCycle(OrigMI); in rewriteScheduledInstr() 1175 (CyclePhi <= CycleSched || OrigMI->isPHI())) in rewriteScheduledInstr() 2376 MachineInstr *OrigMI, int UnrollNum, in generatePhi() argument 2380 int StageNum = Schedule.getStage(OrigMI); in generatePhi() 2420 for (MachineOperand &DefMO : OrigMI->defs()) { in generatePhi()
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H A D | InlineSpiller.cpp | 649 RM.OrigMI = LIS.getInstructionFromIndex(OrigVNI->def); in reMaterializeFor() 667 if (RM.OrigMI->canFoldAsLoad() && in reMaterializeFor() 668 foldMemoryOperand(Ops, RM.OrigMI)) { in reMaterializeFor()
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H A D | SplitKit.cpp | 611 RM.OrigMI = LIS.getInstructionFromIndex(OrigVNI->def); in defFromParent()
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H A D | RegisterCoalescer.cpp | 1365 RM.OrigMI = DefMI; in reMaterializeTrivialDef()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86FixupBWInsts.cpp | 84 Register getSuperRegDestIfDead(MachineInstr *OrigMI) const; 183 Register FixupBWInstPass::getSuperRegDestIfDead(MachineInstr *OrigMI) const { in getSuperRegDestIfDead() 185 Register OrigDestReg = OrigMI->getOperand(0).getReg(); in getSuperRegDestIfDead() 244 unsigned Opc = OrigMI->getOpcode(); in getSuperRegDestIfDead() 253 for (auto &MO: OrigMI->implicit_operands()) { in getSuperRegDestIfDead()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | LiveRangeEdit.h | 190 MachineInstr *OrigMI = nullptr; // Instruction defining OrigVNI. It contains member 198 bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,
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H A D | ModuloSchedule.h | 406 void generatePhi(MachineInstr *OrigMI, int UnrollNum,
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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
H A D | LoongArchOptWInstrs.cpp | 98 static bool hasAllNBitUsers(const MachineInstr &OrigMI, in hasAllNBitUsers() argument 105 Worklist.push_back(std::make_pair(&OrigMI, OrigBits)); in hasAllNBitUsers() 315 static bool hasAllWUsers(const MachineInstr &OrigMI, in hasAllWUsers() argument 318 return hasAllNBitUsers(OrigMI, ST, MRI, 32); in hasAllWUsers()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVOptWInstrs.cpp | 119 static bool hasAllNBitUsers(const MachineInstr &OrigMI, in hasAllNBitUsers() argument 126 Worklist.push_back(std::make_pair(&OrigMI, OrigBits)); in hasAllNBitUsers() 344 static bool hasAllWUsers(const MachineInstr &OrigMI, const RISCVSubtarget &ST, in hasAllWUsers() argument 346 return hasAllNBitUsers(OrigMI, ST, MRI, 32); in hasAllWUsers()
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