Lines Matching refs:OrigMI
63 MachineInstr *createDPPInst(MachineInstr &OrigMI, MachineInstr &MovMI,
68 MachineInstr *createDPPInst(MachineInstr &OrigMI, MachineInstr &MovMI,
205 MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI, in createDPPInst() argument
215 auto OrigOp = OrigMI.getOpcode(); in createDPPInst()
235 auto DPPInst = BuildMI(*OrigMI.getParent(), OrigMI, in createDPPInst()
236 OrigMI.getDebugLoc(), TII->get(DPPOp)) in createDPPInst()
237 .setMIFlags(OrigMI.getFlags()); in createDPPInst()
242 if (auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst)) { in createDPPInst()
246 if (auto *SDst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::sdst)) { in createDPPInst()
278 auto *Mod0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0_modifiers); in createDPPInst()
302 auto *Mod1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1_modifiers); in createDPPInst()
314 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in createDPPInst()
335 auto *Mod2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2_modifiers); in createDPPInst()
344 auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2); in createDPPInst()
357 auto *ClampOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::clamp); in createDPPInst()
361 auto *VdstInOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst_in); in createDPPInst()
366 auto *OmodOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::omod); in createDPPInst()
372 if (TII->getNamedOperand(OrigMI, AMDGPU::OpName::op_sel)) { in createDPPInst()
377 if (Mod0 && TII->isVOP3(OrigMI) && !TII->isVOP3P(OrigMI)) in createDPPInst()
388 if (TII->getNamedOperand(OrigMI, AMDGPU::OpName::op_sel_hi)) { in createDPPInst()
405 auto *NegOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::neg_lo); in createDPPInst()
409 auto *NegHiOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::neg_hi); in createDPPInst()
413 auto *ByteSelOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::byte_sel); in createDPPInst()
486 MachineInstr &OrigMI, MachineInstr &MovMI, RegSubRegPair CombOldVGPR, in createDPPInst() argument
490 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in createDPPInst()
495 if (!isIdentityValue(OrigMI.getOpcode(), OldOpndValue)) { in createDPPInst()
507 return createDPPInst(OrigMI, MovMI, CombOldVGPR, CombBCZ, IsShrinkable); in createDPPInst()
635 auto &OrigMI = *Use->getParent(); in combineDPPMov() local
636 LLVM_DEBUG(dbgs() << " try: " << OrigMI); in combineDPPMov()
638 auto OrigOp = OrigMI.getOpcode(); in combineDPPMov()
642 Register FwdReg = OrigMI.getOperand(0).getReg(); in combineDPPMov()
645 if (execMayBeModifiedBeforeAnyUse(*MRI, FwdReg, OrigMI)) { in combineDPPMov()
651 unsigned OpNo, E = OrigMI.getNumOperands(); in combineDPPMov()
653 if (OrigMI.getOperand(OpNo).getReg() == DPPMovReg) { in combineDPPMov()
654 FwdSubReg = OrigMI.getOperand(OpNo + 1).getImm(); in combineDPPMov()
666 RegSeqWithOpNos[&OrigMI].push_back(OpNo); in combineDPPMov()
670 bool IsShrinkable = isShrinkable(OrigMI); in combineDPPMov()
679 if (OrigMI.modifiesRegister(AMDGPU::EXEC, ST->getRegisterInfo())) { in combineDPPMov()
684 auto *Src0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0); in combineDPPMov()
685 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in combineDPPMov()
686 if (Use != Src0 && !(Use == Src1 && OrigMI.isCommutable())) { // [1] in combineDPPMov()
691 auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2); in combineDPPMov()
699 << " " << OrigMI in combineDPPMov()
704 LLVM_DEBUG(dbgs() << " combining: " << OrigMI); in combineDPPMov()
706 if (auto *DPPInst = createDPPInst(OrigMI, MovMI, CombOldVGPR, in combineDPPMov()
712 assert(Use == Src1 && OrigMI.isCommutable()); // by check [1] in combineDPPMov()
713 auto *BB = OrigMI.getParent(); in combineDPPMov()
714 auto *NewMI = BB->getParent()->CloneMachineInstr(&OrigMI); in combineDPPMov()
715 BB->insert(OrigMI, NewMI); in combineDPPMov()
730 OrigMIs.push_back(&OrigMI); in combineDPPMov()