| /freebsd/contrib/llvm-project/clang/lib/Sema/ |
| H A D | SemaAMDGPU.cpp | 98 auto Ord = ArgResult.Val.getInt().getZExtValue(); in CheckAMDGCNBuiltinFunctionCall() local
102 if (!llvm::isValidAtomicOrderingCABI(Ord)) in CheckAMDGCNBuiltinFunctionCall()
106 switch (static_cast<llvm::AtomicOrderingCABI>(Ord)) { in CheckAMDGCNBuiltinFunctionCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 931 AtomicOrdering Ord) const override;
934 AtomicOrdering Ord) const override;
937 AtomicOrdering Ord) const override;
939 AtomicOrdering Ord) const override;
953 AtomicOrdering Ord) const override;
958 AtomicOrdering Ord) const override;
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| H A D | PPCISelLowering.cpp | 12764 AtomicOrdering Ord) const { in emitLoadLinked()
12798 AtomicOrdering Ord) const { in emitStoreConditional()
12836 AtomicOrdering Ord) const { in emitLeadingFence()
12837 if (Ord == AtomicOrdering::SequentiallyConsistent) in emitLeadingFence()
12839 if (isReleaseOrStronger(Ord)) in emitLeadingFence()
12846 AtomicOrdering Ord) const { in emitTrailingFence()
12847 if (Inst->hasAtomicLoad() && isAcquireOrStronger(Ord)) { in emitTrailingFence()
19819 Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const { in emitMaskedAtomicRMWIntrinsic()
19841 Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const { in emitMaskedAtomicCmpXchgIntrinsic()
19855 emitLeadingFence(Builder, CI, Ord); in emitMaskedAtomicCmpXchgIntrinsic()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LocalStackSlotAllocation.cpp | 62 FrameRef(MachineInstr *I, int64_t Offset, int Idx, unsigned Ord) : in FrameRef() argument
63 MI(I), LocalOffset(Offset), FrameIdx(Idx), Order(Ord) {} in FrameRef()
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| H A D | TargetLoweringBase.cpp | 2390 AtomicOrdering Ord) const { in emitLeadingFence()
2391 if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore()) in emitLeadingFence()
2392 return Builder.CreateFence(Ord); in emitLeadingFence()
2399 AtomicOrdering Ord) const { in emitTrailingFence()
2400 if (isAcquireOrStronger(Ord)) in emitTrailingFence()
2401 return Builder.CreateFence(Ord); in emitTrailingFence()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.h | 267 AtomicOrdering Ord) const override;
269 AtomicOrdering Ord) const override;
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| H A D | NVPTXISelLowering.cpp | 6302 AtomicOrdering Ord) const { in emitLeadingFence()
6304 return TargetLoweringBase::emitLeadingFence(Builder, Inst, Ord); in emitLeadingFence()
6308 if (isReleaseOrStronger(Ord)) in emitLeadingFence()
6309 return Ord == AtomicOrdering::SequentiallyConsistent in emitLeadingFence()
6318 AtomicOrdering Ord) const { in emitTrailingFence()
6321 return TargetLoweringBase::emitTrailingFence(Builder, Inst, Ord); in emitTrailingFence()
6328 if (isAcquireOrStronger(Ord) && in emitTrailingFence()
6329 (Ord != AtomicOrdering::SequentiallyConsistent || in emitTrailingFence()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.h | 236 AtomicOrdering Ord) const override;
238 AtomicOrdering Ord) const override;
318 AtomicOrdering Ord) const override;
325 AtomicOrdering Ord) const override;
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| H A D | RISCVISelLowering.cpp | 23353 AtomicOrdering Ord) const { in emitLeadingFence()
23355 if (isa<LoadInst>(Inst) && Ord == AtomicOrdering::SequentiallyConsistent) in emitLeadingFence()
23356 return Builder.CreateFence(Ord); in emitLeadingFence()
23360 if (isa<LoadInst>(Inst) && Ord == AtomicOrdering::SequentiallyConsistent) in emitLeadingFence()
23361 return Builder.CreateFence(Ord); in emitLeadingFence()
23362 if (isa<StoreInst>(Inst) && isReleaseOrStronger(Ord)) in emitLeadingFence()
23369 AtomicOrdering Ord) const { in emitTrailingFence()
23371 if (isa<StoreInst>(Inst) && Ord == AtomicOrdering::SequentiallyConsistent) in emitTrailingFence()
23372 return Builder.CreateFence(Ord); in emitTrailingFence()
23376 if (isa<LoadInst>(Inst) && isAcquireOrStronger(Ord)) in emitTrailingFence()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.h | 207 AtomicOrdering Ord) const override;
209 AtomicOrdering Ord) const override;
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| H A D | VEISelLowering.cpp | 1050 AtomicOrdering Ord) const { in emitLeadingFence()
1051 switch (Ord) { in emitLeadingFence()
1071 AtomicOrdering Ord) const { in emitTrailingFence()
1072 switch (Ord) { in emitTrailingFence()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 670 AtomicOrdering Ord) const override;
672 AtomicOrdering Ord) const override;
678 AtomicOrdering Ord) const override;
680 AtomicOrdering Ord) const override;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAGHVX.cpp | 109 Coloring(ArrayRef<Node> Ord) : Order(Ord) { in Coloring()
332 PermNetwork(ArrayRef<ElemType> Ord, unsigned Mult = 1) { in PermNetwork()
333 Order.assign(Ord.data(), Ord.data()+Ord.size()); in PermNetwork()
380 ForwardDeltaNetwork(ArrayRef<ElemType> Ord) : PermNetwork(Ord) {} in ForwardDeltaNetwork()
394 ReverseDeltaNetwork(ArrayRef<ElemType> Ord) : PermNetwork(Ord) {} in ReverseDeltaNetwork()
408 BenesNetwork(ArrayRef<ElemType> Ord) : PermNetwork(Ord, 2) {} in BenesNetwork()
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| H A D | HexagonGenInsert.cpp | 388 : MaxSize(MaxORLSize), Ord(RO) {} in OrderedRegisterList()
415 const RegisterOrdering &Ord; member in __anon7f002ed80311::OrderedRegisterList
444 iterator L = llvm::lower_bound(Seq, VR, Ord); in insert()
457 iterator L = llvm::lower_bound(Seq, VR, Ord); in remove()
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| H A D | HexagonISelLowering.h | 369 AtomicOrdering Ord) const override;
371 AtomicOrdering Ord) const override;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.h | 231 AtomicOrdering Ord) const override;
241 AtomicOrdering Ord) const override;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64A57FPLoadBalancing.cpp | 517 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); in scavengeRegister() local
518 for (auto Reg : Ord) { in scavengeRegister()
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| H A D | AArch64ISelLowering.h | 306 AtomicOrdering Ord) const override;
308 AtomicOrdering Ord) const override;
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| /freebsd/contrib/llvm-project/llvm/lib/ProfileData/Coverage/ |
| H A D | CoverageMapping.cpp | 315 unsigned Ord = 0; in TVIdxBuilder() local
328 Decisions.emplace_back(-Node.Width, Ord++, ID, I); in TVIdxBuilder()
329 assert(Ord == Decisions.size()); in TVIdxBuilder()
358 for (auto [NegWidth, Ord, ID, C] : Decisions) { in TVIdxBuilder()
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| /freebsd/contrib/llvm-project/llvm/lib/ObjectYAML/ |
| H A D | CodeViewYAMLSymbols.cpp | 195 ThunkOrdinal &Ord) { in enumeration() argument
198 io.enumCase(Ord, E.Name.str().c_str(), static_cast<ThunkOrdinal>(E.Value)); in enumeration()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVUtils.cpp | 301 SPIRV::MemorySemantics::MemorySemantics getMemSemantics(AtomicOrdering Ord) { in getMemSemantics() argument
302 switch (Ord) { in getMemSemantics()
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| H A D | SPIRVUtils.h | 231 SPIRV::MemorySemantics::MemorySemantics getMemSemantics(AtomicOrdering Ord);
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 2235 Value *Addr, AtomicOrdering Ord) const { in emitLoadLinked() argument
2242 Value *Addr, AtomicOrdering Ord) const { in emitStoreConditional() argument
2254 AtomicOrdering Ord) const { in emitMaskedAtomicRMWIntrinsic() argument
2293 Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const { in emitMaskedAtomicCmpXchgIntrinsic() argument
2330 AtomicOrdering Ord) const;
2334 AtomicOrdering Ord) const;
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| /freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGExpr.cpp | 3736 for (auto &[Check, Ord] : Checked) { in EmitCheck()
3739 (CGM.getCodeGenOpts().SanitizeSkipHotCutoffs[Ord] > 0)) { in EmitCheck()
3742 llvm::ConstantInt::get(CGM.Int8Ty, Ord)); in EmitCheck()
3747 llvm::Value *&Cond = CGM.getCodeGenOpts().SanitizeTrap.has(Ord) ? TrapCond in EmitCheck()
3748 : CGM.getCodeGenOpts().SanitizeRecover.has(Ord) in EmitCheck()
3753 if (!CGM.getCodeGenOpts().SanitizeMergeHandlers.has(Ord)) in EmitCheck()
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| H A D | CGBuiltin.cpp | 5066 auto Ord = dyn_cast<llvm::ConstantInt>(Order); in EmitBuiltinExpr() local
5068 if (Ord && Scp) { in EmitBuiltinExpr()
5072 switch (Ord->getZExtValue()) { in EmitBuiltinExpr()
5113 if (Ord) { in EmitBuiltinExpr()
5114 switch (Ord->getZExtValue()) { in EmitBuiltinExpr()
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