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Searched refs:Ord (Results 1 – 25 of 28) sorted by relevance

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/freebsd/contrib/llvm-project/clang/lib/Sema/
H A DSemaAMDGPU.cpp77 auto Ord = ArgResult.Val.getInt().getZExtValue(); in CheckAMDGCNBuiltinFunctionCall() local
81 if (!llvm::isValidAtomicOrderingCABI(Ord)) in CheckAMDGCNBuiltinFunctionCall()
85 switch (static_cast<llvm::AtomicOrderingCABI>(Ord)) { in CheckAMDGCNBuiltinFunctionCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.h206 AtomicOrdering Ord) const override;
208 AtomicOrdering Ord) const override;
H A DVEISelLowering.cpp1061 AtomicOrdering Ord) const { in emitLeadingFence()
1062 switch (Ord) { in emitLeadingFence()
1082 AtomicOrdering Ord) const { in emitTrailingFence()
1083 switch (Ord) { in emitTrailingFence()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DLocalStackSlotAllocation.cpp62 FrameRef(MachineInstr *I, int64_t Offset, int Idx, unsigned Ord) : in FrameRef() argument
63 MI(I), LocalOffset(Offset), FrameIdx(Idx), Order(Ord) {} in FrameRef()
H A DTargetLoweringBase.cpp2283 AtomicOrdering Ord) const { in emitLeadingFence()
2284 if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore()) in emitLeadingFence()
2285 return Builder.CreateFence(Ord); in emitLeadingFence()
2292 AtomicOrdering Ord) const { in emitTrailingFence()
2293 if (isAcquireOrStronger(Ord)) in emitTrailingFence()
2294 return Builder.CreateFence(Ord); in emitTrailingFence()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.h194 AtomicOrdering Ord) const override;
204 AtomicOrdering Ord) const override;
H A DLoongArchISelLowering.cpp5723 Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const { in emitMaskedAtomicCmpXchgIntrinsic()
5744 Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const { in emitMaskedAtomicRMWIntrinsic()
5755 AI->getAlign(), Ord); in emitMaskedAtomicRMWIntrinsic()
5758 AI->getAlign(), Ord); in emitMaskedAtomicRMWIntrinsic()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.h649 AtomicOrdering Ord) const override;
651 AtomicOrdering Ord) const override;
657 AtomicOrdering Ord) const override;
659 AtomicOrdering Ord) const override;
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVUtils.cpp236 SPIRV::MemorySemantics::MemorySemantics getMemSemantics(AtomicOrdering Ord) { in getMemSemantics() argument
237 switch (Ord) { in getMemSemantics()
H A DSPIRVInstructionSelector.cpp720 static SPIRV::Scope::Scope getScope(SyncScope::ID Ord, in getScope() argument
722 if (Ord == SyncScope::SingleThread || Ord == MMI->Work_ItemSSID) in getScope()
724 else if (Ord == SyncScope::System || Ord == MMI->DeviceSSID) in getScope()
726 else if (Ord == MMI->WorkGroupSSID) in getScope()
728 else if (Ord == MMI->AllSVMDevicesSSID) in getScope()
730 else if (Ord == MMI->SubGroupSSID) in getScope()
966 SyncScope::ID Ord = SyncScope::ID(I.getOperand(1).getImm()); in selectFence() local
967 uint32_t Scope = static_cast<uint32_t>(getScope(Ord, MMI)); in selectFence()
H A DSPIRVUtils.h76 SPIRV::MemorySemantics::MemorySemantics getMemSemantics(AtomicOrdering Ord);
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAGHVX.cpp113 Coloring(ArrayRef<Node> Ord) : Order(Ord) { in Coloring()
337 PermNetwork(ArrayRef<ElemType> Ord, unsigned Mult = 1) { in PermNetwork()
338 Order.assign(Ord.data(), Ord.data()+Ord.size()); in PermNetwork()
385 ForwardDeltaNetwork(ArrayRef<ElemType> Ord) : PermNetwork(Ord) {} in ForwardDeltaNetwork()
399 ReverseDeltaNetwork(ArrayRef<ElemType> Ord) : PermNetwork(Ord) {} in ReverseDeltaNetwork()
[all...]
H A DHexagonGenInsert.cpp387 : MaxSize(MaxORLSize), Ord(RO) {} in OrderedRegisterList()
414 const RegisterOrdering &Ord; member in __anon7f002ed80311::OrderedRegisterList
443 iterator L = llvm::lower_bound(Seq, VR, Ord); in insert()
456 iterator L = llvm::lower_bound(Seq, VR, Ord); in remove()
H A DHexagonISelLowering.h353 AtomicOrdering Ord) const override;
355 AtomicOrdering Ord) const override;
H A DHexagonISelLowering.cpp3865 AtomicOrdering Ord) const { in emitLoadLinked()
3883 AtomicOrdering Ord) const { in emitStoreConditional()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h684 AtomicOrdering Ord) const override;
686 AtomicOrdering Ord) const override;
766 AtomicOrdering Ord) const override;
773 AtomicOrdering Ord) const override;
H A DRISCVISelLowering.cpp20925 AtomicOrdering Ord) const { in emitLeadingFence()
20927 if (isa<LoadInst>(Inst) && Ord == AtomicOrdering::SequentiallyConsistent) in emitLeadingFence()
20928 return Builder.CreateFence(Ord); in emitLeadingFence()
20932 if (isa<LoadInst>(Inst) && Ord == AtomicOrdering::SequentiallyConsistent) in emitLeadingFence()
20933 return Builder.CreateFence(Ord); in emitLeadingFence()
20934 if (isa<StoreInst>(Inst) && isReleaseOrStronger(Ord)) in emitLeadingFence()
20941 AtomicOrdering Ord) const { in emitTrailingFence()
20943 if (isa<StoreInst>(Inst) && Ord == AtomicOrdering::SequentiallyConsistent) in emitTrailingFence()
20944 return Builder.CreateFence(Ord); in emitTrailingFence()
20948 if (isa<LoadInst>(Inst) && isAcquireOrStronger(Ord)) in emitTrailingFence()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h918 AtomicOrdering Ord) const override;
920 AtomicOrdering Ord) const override;
934 AtomicOrdering Ord) const override;
939 AtomicOrdering Ord) const override;
H A DPPCISelLowering.cpp12005 AtomicOrdering Ord) const { in emitLeadingFence()
12006 if (Ord == AtomicOrdering::SequentiallyConsistent) in emitLeadingFence()
12008 if (isReleaseOrStronger(Ord)) in emitLeadingFence()
12015 AtomicOrdering Ord) const { in emitTrailingFence()
12016 if (Inst->hasAtomicLoad() && isAcquireOrStronger(Ord)) { in emitTrailingFence()
18815 Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const { in emitMaskedAtomicRMWIntrinsic()
18837 Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const { in emitMaskedAtomicCmpXchgIntrinsic()
18851 emitLeadingFence(Builder, CI, Ord); in emitMaskedAtomicCmpXchgIntrinsic()
18854 emitTrailingFence(Builder, CI, Ord); in emitMaskedAtomicCmpXchgIntrinsic()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64A57FPLoadBalancing.cpp518 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); in scavengeRegister()
519 for (auto Reg : Ord) { in scavengeRegister() local
H A DAArch64ISelLowering.h785 AtomicOrdering Ord) const override;
787 AtomicOrdering Ord) const override;
H A DAArch64FastISel.cpp2192 AtomicOrdering Ord = SI->getOrdering(); in selectStore() local
2194 if (isReleaseOrStronger(Ord)) { in selectStore()
/freebsd/contrib/llvm-project/llvm/lib/ProfileData/Coverage/
H A DCoverageMapping.cpp259 unsigned Ord = 0; in TVIdxBuilder() local
272 Decisions.emplace_back(-Node.Width, Ord++, ID, I); in TVIdxBuilder()
273 assert(Ord == Decisions.size()); in TVIdxBuilder()
302 for (auto [NegWidth, Ord, ID, C] : Decisions) { in TVIdxBuilder()
/freebsd/contrib/llvm-project/llvm/lib/ObjectYAML/
H A DCodeViewYAMLSymbols.cpp195 ThunkOrdinal &Ord) { in enumeration() argument
198 io.enumCase(Ord, E.Name.str().c_str(), static_cast<ThunkOrdinal>(E.Value)); in enumeration()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h2166 Value *Addr, AtomicOrdering Ord) const { in emitLoadLinked() argument
2173 Value *Addr, AtomicOrdering Ord) const { in emitStoreConditional() argument
2185 AtomicOrdering Ord) const { in emitMaskedAtomicRMWIntrinsic() argument
2219 Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const { in emitMaskedAtomicCmpXchgIntrinsic() argument
2256 AtomicOrdering Ord) const;
2260 AtomicOrdering Ord) const;

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