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Searched refs:OpSize32 (Results 1 – 16 of 16) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrControl.td24 "ret{l}", []>, OpSize32, Requires<[Not64BitMode]>;
26 "ret{q}", []>, OpSize32, Requires<[In64BitMode]>;
30 "ret{l}\t$amt", []>, OpSize32, Requires<[Not64BitMode]>;
32 "ret{q}\t$amt", []>, OpSize32, Requires<[In64BitMode]>;
36 "{l}ret{l|f}", []>, OpSize32;
42 "{l}ret{l|f}\t$amt", []>, OpSize32;
53 def IRET32 : I <0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>, OpSize32;
68 "jmp\t$dst", []>, OpSize32;
87 []>, TB, OpSize32;
119 OpSize32, Sched<[WriteJump]>;
[all …]
H A DX86InstrExtension.td19 "{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>;
31 "{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>;
50 OpSize32, Sched<[WriteALU]>;
54 OpSize32, Sched<[WriteLoad]>;
58 OpSize32, Sched<[WriteALU]>;
62 OpSize32, TB, Sched<[WriteLoad]>;
76 OpSize32, Sched<[WriteALU]>;
80 OpSize32, Sched<[WriteLoad]>;
84 OpSize32, Sched<[WriteALU]>;
88 TB, OpSize32, Sched<[WriteLoad]>;
[all …]
H A DX86InstrShiftRotate.td26 def 32ri : BinOpRI8U_R<m, RegMRM, Xi32, node>, Sched<[ri]>, DefEFLAGS, OpSize32;
45 def 32mi : BinOpMI8U_M<m, MemMRM, Xi32, node>, Sched<[mi, WriteRMW]>, DefEFLAGS, OpSize32;
63 def 32r1 : UnaryOpR_RF<0xD1, RegMRM, m, Xi32>, OpSize32;
88 def 32m1 : UnaryOpM_MF<0xD1, MemMRM, m, Xi32>, OpSize32;
110 def 32rCL : BinOpRC_R<m, RegMRM, Xi32, node>, Sched<[rCL]>, OpSize32;
128 def 32mCL : BinOpMC_M<m, MemMRM, Xi32, node>, Sched<[mCL, WriteRMW]>, OpSize32;
412 def 32rri8 : ShlrdOpRRI8U_R<o1, m, Xi32, node>, TB, DefEFLAGS, OpSize32;
416 def 32rrCL : ShlrdOpRRC_R<o2, m, Xi32, node>, TB, DefEFLAGS, OpSize32;
456 def 32mri8 : ShlrdOpMRI8U_M<o1, m, Xi32, node>, DefEFLAGS, OpSize32;
460 def 32mrCL : ShlrdOpMRC_M<o2, m, Xi32, node>, DefEFLAGS, OpSize32;
[all...]
H A DX86InstrMisc.td23 "nop{l}\t$zero", []>, TB, OpSize32;
30 "nop{l}\t$zero", []>, TB, OpSize32;
64 OpSize32, Requires<[Not64BitMode]>;
70 OpSize32, Requires<[Not64BitMode]>;
77 OpSize32, Requires<[Not64BitMode]>;
84 OpSize32, Requires<[Not64BitMode]>;
90 OpSize32, Requires<[Not64BitMode]>;
99 "push{l}\t$imm", []>, OpSize32,
102 "push{l}\t$imm", []>, OpSize32,
110 OpSize32, Requires<[Not64BitMode]>;
[all …]
H A DX86InstrSystem.td30 "ud1{l}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize32;
37 "ud1{l}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize32;
97 OpSize32;
107 "in{l}\t{$port, %eax|eax, $port}", []>, OpSize32;
116 OpSize32;
126 "out{l}\t{%eax, $port|$port, eax}", []>, OpSize32;
199 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
209 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
244 OpSize32;
247 OpSize32;
[all …]
H A DX86InstrArithmetic.td26 OpSize32, Requires<[Not64BitMode]>;
32 OpSize32, Requires<[In64BitMode]>;
80 def 32r : MulDivOpR<o, RegMRM, m, Xi32, WriteIMul32, []>, OpSize32;
89 def 32m : MulDivOpM<o, MemMRM, m, Xi32, WriteIMul32, []>, OpSize32;
143 def 32r : MulDivOpR<o, RegMRM, m, Xi32, sched32, []>, OpSize32;
151 def 32m : MulDivOpM<o, MemMRM, m, Xi32, sched32, []>, OpSize32;
224 def IMUL32rr : IMulOpRR_RF<Xi32, WriteIMul32Reg>, TB, OpSize32;
227 def IMUL32rm : IMulOpRM_RF<Xi32, WriteIMul32Reg>, TB, OpSize32;
298 def IMUL32rri8 : IMulOpRI8_R<Xi32, WriteIMul32Imm>, DefEFLAGS, OpSize32;
301 def IMUL32rri : IMulOpRI_RF<Xi32, WriteIMul32Imm>, OpSize32;
[all …]
H A DX86InstrTSX.td31 "xbegin\t$dst", []>, OpSize32;
H A DX86InstrCompiler.td382 [(X86rep_movs i32)]>, REP, AdSize32, OpSize32,
401 [(X86rep_movs i32)]>, REP, AdSize64, OpSize32,
424 [(X86rep_stos i32)]>, REP, AdSize32, OpSize32,
447 [(X86rep_stos i32)]>, REP, AdSize64, OpSize32,
692 Requires<[Not64BitMode]>, OpSize32, LOCK,
725 OpSize32, LOCK;
750 OpSize32, LOCK;
781 OpSize32, LOCK;
814 OpSize32, LOCK;
827 OpSize32, LOCK;
[all …]
H A DX86InstrCMovSetCC.td69 defm CMOV32 : Cmov<Xi32, binop_args>, OpSize32, TB;
H A DX86InstrFormats.td186 def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
H A DX86InstrUtils.td20 class OpSize32 { OperandSize OpSize = OpSize32; }
H A DX86InstrSSE.td5811 defm POPCNT32 : Lzcnt<0xB8, "popcnt", ctpop, Xi32, WritePOPCNT, WritePOPCNT.Folded>, OpSize32, XS;
6713 def CRC32r32r32 : Crc32r<Xi32, GR32, int_x86_sse42_crc32_32_32>, OpSize32;
6714 def CRC32r32m32 : Crc32m<Xi32, GR32, int_x86_sse42_crc32_32_32>, OpSize32;
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DX86RecognizableInstr.h175 enum { OpSize16 = 1, OpSize32 = 2 }; enumerator
H A DX86RecognizableInstr.cpp1008 } else if (OpSize == X86Local::OpSize32) { in typeFromString()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86BaseInfo.h702 OpSize32 = 2 << OpSizeShift, enumerator
H A DX86MCCodeEmitter.cpp1468 (STI.hasFeature(X86::Is16Bit) ? X86II::OpSize32 : X86II::OpSize16)) in emitOpcodePrefix()