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Searched refs:OpSize16 (Results 1 – 16 of 16) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrControl.td28 "ret{w}", []>, OpSize16;
34 "ret{w}\t$amt", []>, OpSize16;
40 "{l}ret{w|f}", []>, OpSize16;
46 "{l}ret{w|f}\t$amt", []>, OpSize16;
52 OpSize16;
66 "jmp\t$dst", []>, OpSize16;
83 []>, OpSize16, TB;
112 OpSize16, Sched<[WriteJump]>;
115 OpSize16, Sched<[WriteJumpLd]>;
146 OpSize16, Sched<[WriteJump]>, NOTRACK;
[all …]
H A DX86InstrShiftRotate.td25 def 16ri : BinOpRI8U_R<m, RegMRM, Xi16, node>, Sched<[ri]>, DefEFLAGS, OpSize16;
44 def 16mi : BinOpMI8U_M<m, MemMRM, Xi16, node>, Sched<[mi, WriteRMW]>, DefEFLAGS, OpSize16;
62 def 16r1 : UnaryOpR_RF<0xD1, RegMRM, m, Xi16>, OpSize16;
87 def 16m1 : UnaryOpM_MF<0xD1, MemMRM, m, Xi16>, OpSize16;
109 def 16rCL : BinOpRC_R<m, RegMRM, Xi16, node>, Sched<[rCL]>, OpSize16;
127 def 16mCL : BinOpMC_M<m, MemMRM, Xi16, node>, Sched<[mCL, WriteRMW]>, OpSize16;
411 def 16rri8 : ShlrdOpRRI8U_R<o1, m, Xi16, t_node>, TB, DefEFLAGS, OpSize16;
415 def 16rrCL : ShlrdOpRRC_R<o2, m, Xi16, t_node>, TB, DefEFLAGS, OpSize16;
455 def 16mri8 : ShlrdOpMRI8U_M<o1, m, Xi16, t_node>, DefEFLAGS, OpSize16;
459 def 16mrCL : ShlrdOpMRC_M<o2, m, Xi16, t_node>, DefEFLAGS, OpSize16;
[all...]
H A DX86InstrExtension.td16 "{cbtw|cbw}", []>, OpSize16, Sched<[WriteALU]>;
28 "{cwtd|cwd}", []>, OpSize16, Sched<[WriteALU]>;
41 TB, OpSize16, Sched<[WriteALU]>;
45 TB, OpSize16, Sched<[WriteLoad]>;
67 TB, OpSize16, Sched<[WriteALU]>;
71 TB, OpSize16, Sched<[WriteLoad]>;
96 []>, TB, OpSize16, Sched<[WriteALU]>;
99 []>, TB, OpSize16, Sched<[WriteALU]>;
103 []>, OpSize16, TB, Sched<[WriteLoad]>;
106 []>, TB, OpSize16, Sched<[WriteLoad]>;
[all …]
H A DX86InstrMisc.td21 "nop{w}\t$zero", []>, TB, OpSize16;
28 "nop{w}\t$zero", []>, TB, OpSize16;
62 OpSize16;
68 OpSize16;
75 OpSize16;
82 OpSize16;
88 OpSize16;
94 "push{w}\t$imm", []>, OpSize16;
96 "push{w}\t$imm", []>, OpSize16;
108 OpSize16;
[all …]
H A DX86InstrSystem.td28 "ud1{w}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize16;
35 "ud1{w}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize16;
94 OpSize16;
104 "in{w}\t{$port, %ax|ax, $port}", []>, OpSize16;
113 OpSize16;
123 "out{w}\t{%ax, $port|$port, ax}", []>, OpSize16;
197 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16;
207 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16;
236 OpSize16;
239 OpSize16;
[all …]
H A DX86InstrArithmetic.td20 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize16;
78 def 16r : MulDivOpR<o, RegMRM, m, Xi16, WriteIMul16, []>, OpSize16;
87 def 16m : MulDivOpM<o, MemMRM, m, Xi16, WriteIMul16, []>, OpSize16;
141 def 16r : MulDivOpR<o, RegMRM, m, Xi16, sched16, []>, OpSize16;
149 def 16m : MulDivOpM<o, MemMRM, m, Xi16, sched16, []>, OpSize16;
223 def IMUL16rr : IMulOpRR_RF<Xi16, WriteIMul16Reg>, TB, OpSize16;
226 def IMUL16rm : IMulOpRM_RF<Xi16, WriteIMul16Reg>, TB, OpSize16;
297 def IMUL16rri8 : IMulOpRI8_R<Xi16, WriteIMul16Imm>, DefEFLAGS, OpSize16;
300 def IMUL16rri : IMulOpRI_RF<Xi16, WriteIMul16Imm>, OpSize16;
303 def IMUL16rmi8 : IMulOpMI8_R<Xi16, WriteIMul16Imm>, DefEFLAGS, OpSize16;
[all …]
H A DX86InstrTSX.td29 "xbegin\t$dst", []>, OpSize16;
H A DX86InstrCompiler.td378 [(X86rep_movs i16)]>, REP, AdSize32, OpSize16,
397 [(X86rep_movs i16)]>, REP, AdSize64, OpSize16,
419 [(X86rep_stos i16)]>, REP, AdSize32, OpSize16,
442 [(X86rep_stos i16)]>, REP, AdSize64, OpSize16,
717 OpSize16, LOCK;
742 OpSize16, LOCK;
773 OpSize16, LOCK;
810 OpSize16, LOCK;
823 OpSize16, LOCK;
885 OpSize16, TB, LOCK;
[all …]
H A DX86InstrCMovSetCC.td68 defm CMOV16 : Cmov<Xi16, binop_args>, OpSize16, TB;
H A DX86InstrFormats.td185 def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32/64-bit mode.
H A DX86InstrUtils.td19 class OpSize16 { OperandSize OpSize = OpSize16; }
H A DX86InstrSSE.td5810 defm POPCNT16 : Lzcnt<0xB8, "popcnt", ctpop, Xi16, WritePOPCNT, WritePOPCNT.Folded>, OpSize16, XS;
6711 def CRC32r32r16 : Crc32r<Xi16, GR32, int_x86_sse42_crc32_32_16>, OpSize16;
6712 def CRC32r32m16 : Crc32m<Xi16, GR32, int_x86_sse42_crc32_32_16>, OpSize16;
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DX86RecognizableInstr.cpp338 if (HasREX_W && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)) in insnContext()
342 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) in insnContext()
344 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) in insnContext()
348 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32) in insnContext()
350 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) in insnContext()
369 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) in insnContext()
371 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) in insnContext()
379 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16) in insnContext()
381 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) in insnContext()
1004 if (OpSize == X86Local::OpSize16) { in typeFromString()
[all …]
H A DX86RecognizableInstr.h175 enum { OpSize16 = 1, OpSize32 = 2 }; enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86BaseInfo.h701 OpSize16 = 1 << OpSizeShift, enumerator
H A DX86MCCodeEmitter.cpp1468 (STI.hasFeature(X86::Is16Bit) ? X86II::OpSize32 : X86II::OpSize16)) in emitOpcodePrefix()