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Searched refs:Op1 (Results 1 – 25 of 242) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp217 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { in Decode2OpInstruction() argument
229 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2); in Decode2OpInstruction()
235 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, in Decode3OpInstruction() argument
244 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2); in Decode3OpInstruction()
323 unsigned Op1, Op2; in Decode2RInstruction() local
324 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RInstruction()
328 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); in Decode2RInstruction()
336 unsigned Op1, Op2; in Decode2RImmInstruction() local
337 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RImmInstruction()
341 Inst.addOperand(MCOperand::createImm(Op1)); in Decode2RImmInstruction()
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/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DInstructionSimplify.cpp259 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS); in simplifyAssociativeBinOp() local
282 if (Op1 && Op1->getOpcode() == Opcode) { in simplifyAssociativeBinOp()
284 Value *B = Op1->getOperand(0); in simplifyAssociativeBinOp()
285 Value *C = Op1->getOperand(1); in simplifyAssociativeBinOp()
326 if (Op1 && Op1->getOpcode() == Opcode) { in simplifyAssociativeBinOp()
328 Value *B = Op1->getOperand(0); in simplifyAssociativeBinOp()
329 Value *C = Op1->getOperand(1); in simplifyAssociativeBinOp()
565 Value *&Op0, Value *&Op1, in foldOrCommuteConstant() argument
568 if (auto *CRHS = dyn_cast<Constant>(Op1)) { in foldOrCommuteConstant()
585 std::swap(Op0, Op1); in foldOrCommuteConstant()
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H A DOverflowInstAnalysis.cpp21 bool llvm::isCheckForZeroAndMulWithOverflow(Value *Op0, Value *Op1, bool IsAnd, in isCheckForZeroAndMulWithOverflow() argument
56 matchMulOverflowCheck(Op1)) || in isCheckForZeroAndMulWithOverflow()
58 match(Op1, m_Not(m_Value(NotOp1))) && matchMulOverflowCheck(NotOp1)); in isCheckForZeroAndMulWithOverflow()
67 bool llvm::isCheckForZeroAndMulWithOverflow(Value *Op0, Value *Op1, in isCheckForZeroAndMulWithOverflow() argument
70 return isCheckForZeroAndMulWithOverflow(Op0, Op1, IsAnd, Y); in isCheckForZeroAndMulWithOverflow()
/freebsd/sys/contrib/dev/acpica/compiler/
H A Dasltree.c650 ACPI_PARSE_OBJECT *Op1, in TrLinkPeerOp() argument
658 Op1, Op1 ? UtGetOpName(Op1->Asl.ParseOpcode) : NULL, in TrLinkPeerOp()
662 if ((!Op1) && (!Op2)) in TrLinkPeerOp()
665 return (Op1); in TrLinkPeerOp()
672 return (Op1); in TrLinkPeerOp()
675 if (!Op1) in TrLinkPeerOp()
680 if (Op1 == Op2) in TrLinkPeerOp()
684 Op1); in TrLinkPeerOp()
685 AslError (ASL_WARNING, ASL_MSG_COMPILER_INTERNAL, Op1, in TrLinkPeerOp()
687 return (Op1); in TrLinkPeerOp()
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineMulDivRem.cpp190 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in visitMul() local
192 simplifyMulInst(Op0, Op1, I.hasNoSignedWrap(), I.hasNoUnsignedWrap(), in visitMul()
214 if (match(Op1, m_AllOnes())) { in visitMul()
285 if (Op0->hasOneUse() && match(Op1, m_NegatedPower2())) { in visitMul()
290 auto *Op1C = cast<Constant>(Op1); in visitMul()
306 match(Op1, m_APIntAllowPoison(NegPow2C))) { in visitMul()
325 if (match(Op1, m_ImmConstant(MulC))) { in visitMul()
350 if (Op0 == Op1 && match(Op0, m_Intrinsic<Intrinsic::abs>(m_Value(X)))) in visitMul()
359 match(Op1, m_OneUse(m_Intrinsic<Intrinsic::abs>(m_Value(Y), m_One())))) in visitMul()
369 if (match(Op0, m_Neg(m_Value(X))) && match(Op1, m_Constant(Op1C))) in visitMul()
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H A DInstCombineAddSub.cpp811 Value *Op0 = Add.getOperand(0), *Op1 = Add.getOperand(1); in foldNoWrapAdd() local
814 if (!match(Op1, m_Constant(Op1C))) in foldNoWrapAdd()
821 if (match(Op1, m_APInt(C1)) && in foldNoWrapAdd()
857 Value *Op0 = Add.getOperand(0), *Op1 = Add.getOperand(1); in foldAddWithConstant() local
860 if (!match(Op1, m_ImmConstant(Op1C))) in foldAddWithConstant()
877 match(Op1, m_AllOnes())) in foldAddWithConstant()
883 return SelectInst::Create(X, InstCombiner::AddOne(Op1C), Op1); in foldAddWithConstant()
887 return SelectInst::Create(X, InstCombiner::SubOne(Op1C), Op1); in foldAddWithConstant()
905 match(Op1, m_One())) in foldAddWithConstant()
908 if (!match(Op1, m_APInt(C))) in foldAddWithConstant()
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H A DInstCombineAndOrXor.cpp1572 Value *Op0, Value *Op1) { in foldLogicOfIsFPClass() argument
1587 match(Op1, m_OneUse(m_Intrinsic<Intrinsic::is_fpclass>( in foldLogicOfIsFPClass()
1590 (IsRHSClass || matchIsFPClassLikeFCmp(Op1, ClassVal1, ClassMask1)))) && in foldLogicOfIsFPClass()
1615 auto *II = cast<IntrinsicInst>(Op1); in foldLogicOfIsFPClass()
1663 Value *Op0 = BO.getOperand(0), *Op1 = BO.getOperand(1), *X; in reassociateFCmps() local
1664 if (match(Op1, m_FCmp(m_Value(), m_AnyZeroFP()))) in reassociateFCmps()
1665 std::swap(Op0, Op1); in reassociateFCmps()
1672 !match(Op1, m_BinOp(Opcode, m_Value(BO10), m_Value(BO11)))) in reassociateFCmps()
1706 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in matchDeMorgansLaws() local
1709 match(Op1, m_OneUse(m_Not(m_Value(B)))) && in matchDeMorgansLaws()
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H A DInstCombineCompares.cpp700 auto NewICmp = [Cond](GEPNoWrapFlags NW, Value *Op1, Value *Op2) { in foldGEPICmp() argument
703 return new ICmpInst(ICmpInst::getSignedPredicate(Cond), Op1, Op2); in foldGEPICmp()
706 auto *I = new ICmpInst(Cond, Op1, Op2); in foldGEPICmp()
1333 Value *Op0 = Cmp.getOperand(0), *Op1 = Cmp.getOperand(1); in foldICmpWithConstant() local
1336 if (Pred == ICmpInst::ICMP_UGT && match(Op1, m_ConstantInt(CI)) && in foldICmpWithConstant()
1342 Constant *C = dyn_cast<Constant>(Op1); in foldICmpWithConstant()
3051 Value *Op1, IRBuilderBase &Builder, in createLogicFromTable() argument
3065 return HasOneUse ? Builder.CreateNot(Builder.CreateOr(Op0, Op1)) : nullptr; in createLogicFromTable()
3067 return HasOneUse ? Builder.CreateAnd(Builder.CreateNot(Op0), Op1) : nullptr; in createLogicFromTable()
3071 return HasOneUse ? Builder.CreateAnd(Op0, Builder.CreateNot(Op1)) : nullptr; in createLogicFromTable()
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H A DInstCombineShifts.cpp400 Value *Op1 = FirstShiftIsOp1 ? NewShift2 : NewShift1; in foldShiftOfShiftedBinOp() local
402 return BinaryOperator::Create(BinInst->getOpcode(), Op1, Op2); in foldShiftOfShiftedBinOp()
409 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in commonShiftTransforms() local
410 assert(Op0->getType() == Op1->getType()); in commonShiftTransforms()
415 if (match(Op1, m_OneUse(m_SExt(m_Value(Y))))) { in commonShiftTransforms()
416 Value *NewExt = Builder.CreateZExt(Y, Ty, Op1->getName()); in commonShiftTransforms()
426 if (SelectInst *SI = dyn_cast<SelectInst>(Op1)) in commonShiftTransforms()
431 if (match(Op1, m_ImmConstant(CUI))) in commonShiftTransforms()
444 match(Op1, m_NUWAddLike(m_Value(A), m_Constant(C1)))) { in commonShiftTransforms()
464 if (match(Op0, m_APInt(AC)) && match(Op1, m_Add(m_Value(A), m_APInt(AddC))) && in commonShiftTransforms()
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/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DScalarEvolutionPatternMatch.h167 Op1_t Op1; member
169 SCEVBinaryExpr_match(Op0_t Op0, Op1_t Op1) : Op0(Op0), Op1(Op1) {} in SCEVBinaryExpr_match()
174 Op1.match(E->getOperand(1)); in match()
180 m_scev_Binary(const Op0_t &Op0, const Op1_t &Op1) { in m_scev_Binary() argument
181 return SCEVBinaryExpr_match<SCEVTy, Op0_t, Op1_t>(Op0, Op1); in m_scev_Binary()
186 m_scev_Add(const Op0_t &Op0, const Op1_t &Op1) { in m_scev_Add() argument
187 return m_scev_Binary<SCEVAddExpr>(Op0, Op1); in m_scev_Add()
192 m_scev_Mul(const Op0_t &Op0, const Op1_t &Op1) { in m_scev_Mul() argument
193 return m_scev_Binary<SCEVMulExpr>(Op0, Op1); in m_scev_Mul()
198 m_scev_UDiv(const Op0_t &Op0, const Op1_t &Op1) { in m_scev_UDiv() argument
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DVPlanPatternMatch.h333 m_VPInstruction(const Op0_t &Op0, const Op1_t &Op1) { in m_VPInstruction() argument
334 return BinaryVPInstruction_match<Op0_t, Op1_t, Opcode>(Op0, Op1); in m_VPInstruction()
339 m_VPInstruction(const Op0_t &Op0, const Op1_t &Op1, const Op2_t &Op2) { in m_VPInstruction() argument
341 {Op0, Op1, Op2}); in m_VPInstruction()
358 m_VPInstruction(const Op0_t &Op0, const Op1_t &Op1, const Op2_t &Op2, in m_VPInstruction() argument
361 {Op0, Op1, Op2, Op3}); in m_VPInstruction()
383 m_ActiveLaneMask(const Op0_t &Op0, const Op1_t &Op1) { in m_ActiveLaneMask() argument
384 return m_VPInstruction<VPInstruction::ActiveLaneMask>(Op0, Op1); in m_ActiveLaneMask()
389 m_BranchOnCount(const Op0_t &Op0, const Op1_t &Op1) { in m_BranchOnCount() argument
390 return m_VPInstruction<VPInstruction::BranchOnCount>(Op0, Op1); in m_BranchOnCount()
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/freebsd/contrib/llvm-project/clang/lib/CodeGen/TargetBuiltins/
H A DPPC.cpp364 Value *Op1 = EmitScalarExpr(E->getArg(1)); in EmitPPCBuiltinExpr() local
365 int64_t NumBytes = cast<ConstantInt>(Op1)->getZExtValue(); in EmitPPCBuiltinExpr()
388 Int8Ty, Op0, ConstantInt::get(Op1->getType(), NumBytes - 1)); in EmitPPCBuiltinExpr()
394 Op1 = IsLE ? LoLd : HiLd; in EmitPPCBuiltinExpr()
395 Value *AllElts = Builder.CreateCall(Vperm, {Op0, Op1, Mask1}, "shuffle1"); in EmitPPCBuiltinExpr()
417 Value *Op1 = EmitScalarExpr(E->getArg(1)); in EmitPPCBuiltinExpr() local
419 int64_t NumBytes = cast<ConstantInt>(Op1)->getZExtValue(); in EmitPPCBuiltinExpr()
537 Value *Op1 = EmitScalarExpr(E->getArg(1)); in EmitPPCBuiltinExpr() local
589 Builder.CreateCall(CGM.getIntrinsic(ID), {Op0, Op1, Op2}), ResultType); in EmitPPCBuiltinExpr()
594 Value *Op1 = EmitScalarExpr(E->getArg(1)); in EmitPPCBuiltinExpr() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp337 const MachineOperand &Op1 = MI->getOperand(1); in profit() local
339 int32_t Prof1 = Op1.isImm() ? profitImm(Op1.getImm()) : 0; in profit()
692 MachineOperand &Op1 = MI->getOperand(1); in splitImmediate() local
693 assert(Op0.isReg() && Op1.isImm()); in splitImmediate()
694 uint64_t V = Op1.getImm(); in splitImmediate()
719 MachineOperand &Op1 = MI->getOperand(1); in splitCombine() local
729 if (!Op1.isReg()) { in splitCombine()
731 .add(Op1); in splitCombine()
734 .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg()); in splitCombine()
749 MachineOperand &Op1 = MI->getOperand(1); in splitExt() local
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H A DHexagonMask.cpp52 const MachineOperand &Op1 = MI.getOperand(1); in replaceConstExtTransferImmWithMask() local
53 if (!Op1.isImm()) in replaceConstExtTransferImmWithMask()
55 int32_t V = Op1.getImm(); in replaceConstExtTransferImmWithMask()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DDFAPacketizer.cpp252 bool VLIWPacketizerList::alias(const MachineMemOperand &Op1, in alias() argument
255 if (!Op1.getValue() || !Op2.getValue() || !Op1.getSize().hasValue() || in alias()
259 int64_t MinOffset = std::min(Op1.getOffset(), Op2.getOffset()); in alias()
260 int64_t Overlapa = Op1.getSize().getValue() + Op1.getOffset() - MinOffset; in alias()
264 AA->alias(MemoryLocation(Op1.getValue(), Overlapa, in alias()
265 UseTBAA ? Op1.getAAInfo() : AAMDNodes()), in alias()
278 for (const MachineMemOperand *Op1 : MI1.memoperands()) in alias() local
280 if (alias(*Op1, *Op2, UseTBAA)) in alias()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.cpp157 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local
160 Ops[2].getAsInteger(10, Op1); in parseGenericRegister()
164 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; in parseGenericRegister()
172 uint32_t Op1 = (Bits >> 11) & 0x7; in genericRegisterString() local
177 return "S" + utostr(Op0) + "_" + utostr(Op1) + "_C" + utostr(CRn) + "_C" + in genericRegisterString()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DConstraintElimination.cpp79 Value *Op1 = nullptr; member
82 ConditionTy(CmpPredicate Pred, Value *Op0, Value *Op1) in ConditionTy()
83 : Pred(Pred), Op0(Op0), Op1(Op1) {} in ConditionTy()
123 FactOrCheck(DomTreeNode *DTN, CmpPredicate Pred, Value *Op0, Value *Op1, in FactOrCheck()
125 : Cond(Pred, Op0, Op1), DoesHold(Precond), NumIn(DTN->getDFSNumIn()),
129 Value *Op0, Value *Op1, in getConditionFact()
131 return FactOrCheck(DTN, Pred, Op0, Op1, Precond);
301 ConstraintTy getConstraint(CmpInst::Predicate Pred, Value *Op0, Value *Op1,
313 Value *Op1) const;
530 Value *Op1; in decompose() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiMCCodeEmitter.cpp187 const MCOperand Op1 = Inst.getOperand(OpNo + 0); in getRiMemoryOpValue() local
191 assert(Op1.isReg() && "First operand is not register."); in getRiMemoryOpValue()
197 Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 18); in getRiMemoryOpValue()
219 const MCOperand Op1 = Inst.getOperand(OpNo + 0); in getRrMemoryOpValue() local
223 assert(Op1.isReg() && "First operand is not register."); in getRrMemoryOpValue()
224 Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 15); in getRrMemoryOpValue()
258 const MCOperand Op1 = Inst.getOperand(OpNo + 0); in getSplsOpValue() local
262 assert(Op1.isReg() && "First operand is not register."); in getSplsOpValue()
268 Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 12); in getSplsOpValue()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DBypassSlowDivision.cpp86 Value *insertOperandRuntimeCheck(Value *Op1, Value *Op2);
200 Value *Op1 = I->getOperand(1); in isHashLikeValue() local
201 ConstantInt *C = dyn_cast<ConstantInt>(Op1); in isHashLikeValue()
202 if (!C && isa<BitCastInst>(Op1)) in isHashLikeValue()
203 C = dyn_cast<ConstantInt>(cast<BitCastInst>(Op1)->getOperand(0)); in isHashLikeValue()
327 Value *FastDivInsertionTask::insertOperandRuntimeCheck(Value *Op1, Value *Op2) { in insertOperandRuntimeCheck() argument
328 assert((Op1 || Op2) && "Nothing to check"); in insertOperandRuntimeCheck()
333 if (Op1 && Op2) in insertOperandRuntimeCheck()
334 OrV = Builder.CreateOr(Op1, Op2); in insertOperandRuntimeCheck()
336 OrV = Op1 ? Op1 : Op2; in insertOperandRuntimeCheck()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCBranchCoalescing.cpp338 const MachineOperand &Op1 = OpList1[i]; in identicalOperands() local
341 LLVM_DEBUG(dbgs() << "Op1: " << Op1 << "\n" in identicalOperands()
344 if (Op1.isIdenticalTo(Op2)) { in identicalOperands()
346 if (Op1.isReg() && Op1.getReg().isPhysical() in identicalOperands()
349 && !(Op1.isUse() && MRI->isConstantPhysReg(Op1.getReg()))) { in identicalOperands()
360 if (Op1.isReg() && Op2.isReg() && Op1.getReg().isVirtual() && in identicalOperands()
362 MachineInstr *Op1Def = MRI->getVRegDef(Op1.getReg()); in identicalOperands()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DPatternMatch.h1759 T0 Op1; member
1761 OneOps_match(const T0 &Op1) : Op1(Op1) {} in OneOps_match()
1766 return Op1.match(I->getOperand(0)); in match()
1774 T0 Op1; member
1777 TwoOps_match(const T0 &Op1, const T1 &Op2) : Op1(Op1), Op2(Op2) {} in TwoOps_match()
1782 return Op1.match(I->getOperand(0)) && Op2.match(I->getOperand(1)); in match()
1792 T0 Op1; member
1796 ThreeOps_match(const T0 &Op1, const T1 &Op2, const T2 &Op3) in ThreeOps_match()
1797 : Op1(Op1), Op2(Op2), Op3(Op3) {} in ThreeOps_match()
1802 if (!Op1.match(I->getOperand(0))) in match()
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/freebsd/contrib/llvm-project/llvm/lib/MC/MCParser/
H A DMCTargetAsmParser.cpp53 bool MCTargetAsmParser::areEqualRegs(const MCParsedAsmOperand &Op1, in areEqualRegs() argument
55 return Op1.isReg() && Op2.isReg() && Op1.getReg() == Op2.getReg(); in areEqualRegs()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblySelectionDAGInfo.h29 SDValue Chain, SDValue Op1, SDValue Op2,
36 SDValue Op1, SDValue Op2, SDValue Op3,
41 SDValue Chain, SDValue Op1, SDValue Op2,
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiMemAluCombiner.cpp163 bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) { in isSameOperand() argument
164 if (Op1.getType() != Op2.getType()) in isSameOperand()
167 switch (Op1.getType()) { in isSameOperand()
169 return Op1.getReg() == Op2.getReg(); in isSameOperand()
171 return Op1.getImm() == Op2.getImm(); in isSameOperand()
286 MachineOperand &Op1 = AluIter->getOperand(1); in isSuitableAluInstr() local
291 if (!isSameOperand(Dest, Base) || !isSameOperand(Dest, Op1)) in isSuitableAluInstr()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGTargetInfo.h76 SDValue Chain, SDValue Op1, in EmitTargetCodeForMemcpy() argument
92 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, in EmitTargetCodeForMemmove() argument
106 SDValue Chain, SDValue Op1, in EmitTargetCodeForMemset() argument
120 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp() argument
157 SDValue Op1, SDValue Op2, in EmitTargetCodeForStrcmp() argument

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