| /freebsd/contrib/llvm-project/llvm/lib/Target/XCore/Disassembler/ |
| H A D | XCoreDisassembler.cpp | 216 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { in Decode2OpInstruction() argument
228 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2); in Decode2OpInstruction()
234 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, in Decode3OpInstruction() argument
243 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2); in Decode3OpInstruction()
322 unsigned Op1, Op2; in Decode2RInstruction() local
323 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RInstruction()
327 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); in Decode2RInstruction()
335 unsigned Op1, Op2; in Decode2RImmInstruction() local
336 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RImmInstruction()
340 Inst.addOperand(MCOperand::createImm(Op1)); in Decode2RImmInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VPlanPatternMatch.h | 164 Op1_t Op1;
166 BinaryRecipe_match(Op0_t Op0, Op1_t Op1) : Op0(Op0), Op1(Op1) {}
182 if (Op0.match(R->getOperand(0)) && Op1.match(R->getOperand(1)))
185 Op1.match(R->getOperand(0));
208 m_VPInstruction(const Op0_t &Op0, const Op1_t &Op1) {
209 return BinaryVPInstruction_match<Op0_t, Op1_t, Opcode>(Op0, Op1);
226 m_ActiveLaneMask(const Op0_t &Op0, const Op1_t &Op1) {
227 return m_VPInstruction<VPInstruction::ActiveLaneMask>(Op0, Op1);
232 m_BranchOnCount(const Op0_t &Op0, const Op1_t &Op1) {
233 return m_VPInstruction<VPInstruction::BranchOnCount>(Op0, Op1);
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineMulDivRem.cpp | 196 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in visitMul() local
198 simplifyMulInst(Op0, Op1, I.hasNoSignedWrap(), I.hasNoUnsignedWrap(), in visitMul()
220 if (match(Op1, m_AllOnes())) { in visitMul()
264 if (Op0->hasOneUse() && match(Op1, m_NegatedPower2())) { in visitMul()
269 auto *Op1C = cast<Constant>(Op1); in visitMul()
285 match(Op1, m_APIntAllowPoison(NegPow2C))) { in visitMul()
304 if (match(Op1, m_ImmConstant(MulC))) { in visitMul()
329 if (Op0 == Op1 && match(Op0, m_Intrinsic<Intrinsic::abs>(m_Value(X)))) in visitMul()
338 match(Op1, m_OneUse(m_Intrinsic<Intrinsic::abs>(m_Value(Y), m_One())))) in visitMul()
348 if (match(Op0, m_Neg(m_Value(X))) && match(Op1, m_Constant(Op1C))) in visitMul()
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| H A D | InstCombineAddSub.cpp | 811 Value *Op0 = Add.getOperand(0), *Op1 = Add.getOperand(1); in foldNoWrapAdd() local
814 if (!match(Op1, m_Constant(Op1C))) in foldNoWrapAdd()
821 if (match(Op1, m_APInt(C1)) && in foldNoWrapAdd()
857 Value *Op0 = Add.getOperand(0), *Op1 = Add.getOperand(1); in foldAddWithConstant() local
860 if (!match(Op1, m_ImmConstant(Op1C))) in foldAddWithConstant()
877 match(Op1, m_AllOnes())) in foldAddWithConstant()
883 return SelectInst::Create(X, InstCombiner::AddOne(Op1C), Op1); in foldAddWithConstant()
887 return SelectInst::Create(X, InstCombiner::SubOne(Op1C), Op1); in foldAddWithConstant()
905 match(Op1, m_One())) in foldAddWithConstant()
908 if (!match(Op1, m_APInt(C))) in foldAddWithConstant()
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| H A D | InstCombineCompares.cpp | 1297 Value *Op0 = Cmp.getOperand(0), *Op1 = Cmp.getOperand(1); in foldICmpWithConstant() local
1300 if (Pred == ICmpInst::ICMP_UGT && match(Op1, m_ConstantInt(CI)) && in foldICmpWithConstant()
1306 Constant *C = dyn_cast<Constant>(Op1); in foldICmpWithConstant()
2970 Value *Op1, IRBuilderBase &Builder, in createLogicFromTable() argument
2984 return HasOneUse ? Builder.CreateNot(Builder.CreateOr(Op0, Op1)) : nullptr; in createLogicFromTable()
2986 return HasOneUse ? Builder.CreateAnd(Builder.CreateNot(Op0), Op1) : nullptr; in createLogicFromTable()
2990 return HasOneUse ? Builder.CreateAnd(Op0, Builder.CreateNot(Op1)) : nullptr; in createLogicFromTable()
2992 return Builder.CreateNot(Op1); in createLogicFromTable()
2994 return Builder.CreateXor(Op0, Op1); in createLogicFromTable()
2996 return HasOneUse ? Builder.CreateNot(Builder.CreateAnd(Op0, Op1)) : nullptr; in createLogicFromTable()
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| H A D | InstCombineAndOrXor.cpp | 1527 Value *Op0, Value *Op1) { in foldLogicOfIsFPClass() argument
1542 match(Op1, m_OneUse(m_Intrinsic<Intrinsic::is_fpclass>( in foldLogicOfIsFPClass()
1545 (IsRHSClass || matchIsFPClassLikeFCmp(Op1, ClassVal1, ClassMask1)))) && in foldLogicOfIsFPClass()
1570 auto *II = cast<IntrinsicInst>(Op1); in foldLogicOfIsFPClass()
1618 Value *Op0 = BO.getOperand(0), *Op1 = BO.getOperand(1), *X; in reassociateFCmps() local
1620 if (match(Op1, m_FCmp(Pred, m_Value(), m_AnyZeroFP()))) in reassociateFCmps()
1621 std::swap(Op0, Op1); in reassociateFCmps()
1628 !match(Op1, m_BinOp(Opcode, m_Value(BO10), m_Value(BO11)))) in reassociateFCmps()
1665 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in matchDeMorgansLaws() local
1668 match(Op1, m_OneUse(m_Not(m_Value(B)))) && in matchDeMorgansLaws()
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| H A D | InstCombineShifts.cpp | 400 Value *Op1 = FirstShiftIsOp1 ? NewShift2 : NewShift1; in foldShiftOfShiftedBinOp() local
402 return BinaryOperator::Create(BinInst->getOpcode(), Op1, Op2); in foldShiftOfShiftedBinOp()
409 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in commonShiftTransforms() local
410 assert(Op0->getType() == Op1->getType()); in commonShiftTransforms()
415 if (match(Op1, m_OneUse(m_SExt(m_Value(Y))))) { in commonShiftTransforms()
416 Value *NewExt = Builder.CreateZExt(Y, Ty, Op1->getName()); in commonShiftTransforms()
426 if (SelectInst *SI = dyn_cast<SelectInst>(Op1)) in commonShiftTransforms()
430 if (Constant *CUI = dyn_cast<Constant>(Op1)) in commonShiftTransforms()
443 match(Op1, m_NUWAddLike(m_Value(A), m_Constant(C1)))) { in commonShiftTransforms()
463 if (match(Op0, m_APInt(AC)) && match(Op1, m_Add(m_Value(A), m_APInt(AddC))) && in commonShiftTransforms()
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | InstructionSimplify.cpp | 301 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS); in simplifyAssociativeBinOp() local
324 if (Op1 && Op1->getOpcode() == Opcode) { in simplifyAssociativeBinOp()
326 Value *B = Op1->getOperand(0); in simplifyAssociativeBinOp()
327 Value *C = Op1->getOperand(1); in simplifyAssociativeBinOp()
368 if (Op1 && Op1->getOpcode() == Opcode) { in simplifyAssociativeBinOp()
370 Value *B = Op1->getOperand(0); in simplifyAssociativeBinOp()
371 Value *C = Op1->getOperand(1); in simplifyAssociativeBinOp()
608 Value *&Op0, Value *&Op1, in foldOrCommuteConstant() argument
611 if (auto *CRHS = dyn_cast<Constant>(Op1)) { in foldOrCommuteConstant()
628 std::swap(Op0, Op1); in foldOrCommuteConstant()
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| H A D | OverflowInstAnalysis.cpp | 21 bool llvm::isCheckForZeroAndMulWithOverflow(Value *Op0, Value *Op1, bool IsAnd, in isCheckForZeroAndMulWithOverflow() argument
56 matchMulOverflowCheck(Op1)) || in isCheckForZeroAndMulWithOverflow()
58 match(Op1, m_Not(m_Value(NotOp1))) && matchMulOverflowCheck(NotOp1)); in isCheckForZeroAndMulWithOverflow()
67 bool llvm::isCheckForZeroAndMulWithOverflow(Value *Op0, Value *Op1, in isCheckForZeroAndMulWithOverflow() argument
70 return isCheckForZeroAndMulWithOverflow(Op0, Op1, IsAnd, Y); in isCheckForZeroAndMulWithOverflow()
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| /freebsd/sys/contrib/dev/acpica/compiler/ |
| H A D | asltree.c | 650 ACPI_PARSE_OBJECT *Op1, in TrLinkPeerOp() argument
658 Op1, Op1 ? UtGetOpName(Op1->Asl.ParseOpcode) : NULL, in TrLinkPeerOp()
662 if ((!Op1) && (!Op2)) in TrLinkPeerOp()
665 return (Op1); in TrLinkPeerOp()
672 return (Op1); in TrLinkPeerOp()
675 if (!Op1) in TrLinkPeerOp()
680 if (Op1 == Op2) in TrLinkPeerOp()
684 Op1); in TrLinkPeerOp()
685 AslError (ASL_WARNING, ASL_MSG_COMPILER_INTERNAL, Op1, in TrLinkPeerOp()
687 return (Op1); in TrLinkPeerOp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSplitDouble.cpp | 343 const MachineOperand &Op1 = MI->getOperand(1); in profit() local
345 int32_t Prof1 = Op1.isImm() ? profitImm(Op1.getImm()) : 0; in profit()
698 MachineOperand &Op1 = MI->getOperand(1); in splitImmediate() local
699 assert(Op0.isReg() && Op1.isImm()); in splitImmediate()
700 uint64_t V = Op1.getImm(); in splitImmediate()
725 MachineOperand &Op1 = MI->getOperand(1); in splitCombine() local
735 if (!Op1.isReg()) { in splitCombine()
737 .add(Op1); in splitCombine()
740 .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg()); in splitCombine()
755 MachineOperand &Op1 = MI->getOperand(1); in splitExt() local
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | DFAPacketizer.cpp | 252 bool VLIWPacketizerList::alias(const MachineMemOperand &Op1, in alias() argument
255 if (!Op1.getValue() || !Op2.getValue() || !Op1.getSize().hasValue() || in alias()
259 int64_t MinOffset = std::min(Op1.getOffset(), Op2.getOffset()); in alias()
260 int64_t Overlapa = Op1.getSize().getValue() + Op1.getOffset() - MinOffset; in alias()
264 AA->alias(MemoryLocation(Op1.getValue(), Overlapa, in alias()
265 UseTBAA ? Op1.getAAInfo() : AAMDNodes()), in alias()
278 for (const MachineMemOperand *Op1 : MI1.memoperands()) in alias() local
280 if (alias(*Op1, *Op2, UseTBAA)) in alias()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.cpp | 158 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local
161 Ops[2].getAsInteger(10, Op1); in parseGenericRegister()
165 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; in parseGenericRegister()
173 uint32_t Op1 = (Bits >> 11) & 0x7; in genericRegisterString() local
178 return "S" + utostr(Op0) + "_" + utostr(Op1) + "_C" + utostr(CRn) + "_C" + in genericRegisterString()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | ConstraintElimination.cpp | 93 Value *Op1; member
96 : Pred(CmpInst::BAD_ICMP_PREDICATE), Op0(nullptr), Op1(nullptr) {} in ConditionTy()
97 ConditionTy(CmpInst::Predicate Pred, Value *Op0, Value *Op1) in ConditionTy()
98 : Pred(Pred), Op0(Op0), Op1(Op1) {} in ConditionTy()
139 FactOrCheck(DomTreeNode *DTN, CmpInst::Predicate Pred, Value *Op0, Value *Op1, in FactOrCheck()
141 : Cond(Pred, Op0, Op1), DoesHold(Precond), NumIn(DTN->getDFSNumIn()), in FactOrCheck()
145 Value *Op0, Value *Op1, in getConditionFact()
147 return FactOrCheck(DTN, Pred, Op0, Op1, Precond); in getConditionFact()
316 ConstraintTy getConstraint(CmpInst::Predicate Pred, Value *Op0, Value *Op1,
327 Value *Op1) const;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
| H A D | LanaiMCCodeEmitter.cpp | 189 const MCOperand Op1 = Inst.getOperand(OpNo + 0); in getRiMemoryOpValue() local
193 assert(Op1.isReg() && "First operand is not register."); in getRiMemoryOpValue()
199 Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 18); in getRiMemoryOpValue()
221 const MCOperand Op1 = Inst.getOperand(OpNo + 0); in getRrMemoryOpValue() local
225 assert(Op1.isReg() && "First operand is not register."); in getRrMemoryOpValue()
226 Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 15); in getRrMemoryOpValue()
260 const MCOperand Op1 = Inst.getOperand(OpNo + 0); in getSplsOpValue() local
264 assert(Op1.isReg() && "First operand is not register."); in getSplsOpValue()
270 Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 12); in getSplsOpValue()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | BypassSlowDivision.cpp | 87 Value *insertOperandRuntimeCheck(Value *Op1, Value *Op2);
201 Value *Op1 = I->getOperand(1); in isHashLikeValue() local
202 ConstantInt *C = dyn_cast<ConstantInt>(Op1); in isHashLikeValue()
203 if (!C && isa<BitCastInst>(Op1)) in isHashLikeValue()
204 C = dyn_cast<ConstantInt>(cast<BitCastInst>(Op1)->getOperand(0)); in isHashLikeValue()
328 Value *FastDivInsertionTask::insertOperandRuntimeCheck(Value *Op1, Value *Op2) { in insertOperandRuntimeCheck() argument
329 assert((Op1 || Op2) && "Nothing to check"); in insertOperandRuntimeCheck()
334 if (Op1 && Op2) in insertOperandRuntimeCheck()
335 OrV = Builder.CreateOr(Op1, Op2); in insertOperandRuntimeCheck()
337 OrV = Op1 ? Op1 : Op2; in insertOperandRuntimeCheck()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAGTargetInfo.h | 52 SDValue Chain, SDValue Op1, in EmitTargetCodeForMemcpy() argument
68 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, in EmitTargetCodeForMemmove() argument
82 SDValue Chain, SDValue Op1, in EmitTargetCodeForMemset() argument
96 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp() argument
133 SDValue Op1, SDValue Op2, in EmitTargetCodeForStrcmp() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCBranchCoalescing.cpp | 340 const MachineOperand &Op1 = OpList1[i]; in identicalOperands() local
343 LLVM_DEBUG(dbgs() << "Op1: " << Op1 << "\n" in identicalOperands()
346 if (Op1.isIdenticalTo(Op2)) { in identicalOperands()
348 if (Op1.isReg() && Op1.getReg().isPhysical() in identicalOperands()
351 && !(Op1.isUse() && MRI->isConstantPhysReg(Op1.getReg()))) { in identicalOperands()
362 if (Op1.isReg() && Op2.isReg() && Op1.getReg().isVirtual() && in identicalOperands()
364 MachineInstr *Op1Def = MRI->getVRegDef(Op1.getReg()); in identicalOperands()
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| /freebsd/contrib/llvm-project/llvm/lib/MC/MCParser/ |
| H A D | MCTargetAsmParser.cpp | 53 bool MCTargetAsmParser::areEqualRegs(const MCParsedAsmOperand &Op1, in areEqualRegs() argument
55 return Op1.isReg() && Op2.isReg() && Op1.getReg() == Op2.getReg(); in areEqualRegs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblySelectionDAGInfo.h | 26 SDValue Chain, SDValue Op1, SDValue Op2,
33 SDValue Op1, SDValue Op2, SDValue Op3,
38 SDValue Chain, SDValue Op1, SDValue Op2,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiMemAluCombiner.cpp | 169 bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) {
170 if (Op1.getType() != Op2.getType()) in isSameOperand() argument
173 switch (Op1.getType()) { in isSameOperand()
175 return Op1.getReg() == Op2.getReg(); in isSameOperand()
177 return Op1.getImm() == Op2.getImm(); in isSameOperand()
292 MachineOperand &Op1 = AluIter->getOperand(1); in isSuitableAluInstr()
297 if (!isSameOperand(Dest, Base) || !isSameOperand(Dest, Op1)) in isSuitableAluInstr()
293 MachineOperand &Op1 = AluIter->getOperand(1); isSuitableAluInstr() local
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | PatternMatch.h | 1663 T0 Op1; member
1665 OneOps_match(const T0 &Op1) : Op1(Op1) {} in OneOps_match()
1670 return Op1.match(I->getOperand(0)); in match()
1678 T0 Op1; member
1681 TwoOps_match(const T0 &Op1, const T1 &Op2) : Op1(Op1), Op2(Op2) {} in TwoOps_match()
1686 return Op1.match(I->getOperand(0)) && Op2.match(I->getOperand(1)); in match()
1695 T0 Op1; member
1699 ThreeOps_match(const T0 &Op1, const T1 &Op2, const T2 &Op3) in ThreeOps_match()
1700 : Op1(Op1), Op2(Op2), Op3(Op3) {} in ThreeOps_match()
1705 return Op1.match(I->getOperand(0)) && Op2.match(I->getOperand(1)) && in match()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIOptimizeExecMaskingPreRA.cpp | 154 MachineOperand *Op1 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src0); in optimizeVcndVcmpPair() local
156 if (Op1->isImm() && Op2->isReg()) in optimizeVcndVcmpPair()
157 std::swap(Op1, Op2); in optimizeVcndVcmpPair()
158 if (!Op1->isReg() || !Op2->isImm() || Op2->getImm() != 1) in optimizeVcndVcmpPair()
161 Register SelReg = Op1->getReg(); in optimizeVcndVcmpPair()
165 auto *Sel = TRI->findReachingDef(SelReg, Op1->getSubReg(), *Cmp, *MRI, LIS); in optimizeVcndVcmpPair()
173 Op1 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src0); in optimizeVcndVcmpPair()
176 if (!Op1->isImm() || !Op2->isImm() || !CC->isReg() || in optimizeVcndVcmpPair()
177 Op1->getImm() != 0 || Op2->getImm() != 1) in optimizeVcndVcmpPair()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SystemOperands.td | 428 // Name, Op1, Op2
452 // Name, Op1, Op2, Crm_high
701 // Op0 Op1 CRn CRm Op2
774 // Op0 Op1 CRn CRm Op2
813 // Op0 Op1 CRn CRm Op2
824 // Op0 Op1 CRn CRm Op2
830 // Op0 Op1 CRn CRm Op2
835 // Op0 Op1 CRn CRm Op2
842 // Op0 Op1 CRn CRm Op2
879 // Op0 Op1 CRn CRm Op2
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.h | 234 void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1);
235 void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1);
506 const SrcOp &Op1,
532 const SrcOp &Op1) { in buildPtrMask() argument
533 return buildInstr(TargetOpcode::G_PTRMASK, {Res}, {Op0, Op1}); in buildPtrMask()
593 const SrcOp &Op0, const SrcOp &Op1) { in buildUAddo() argument
594 return buildInstr(TargetOpcode::G_UADDO, {Res, CarryOut}, {Op0, Op1}); in buildUAddo()
599 const SrcOp &Op0, const SrcOp &Op1) { in buildUSubo() argument
600 return buildInstr(TargetOpcode::G_USUBO, {Res, CarryOut}, {Op0, Op1}); in buildUSubo()
605 const SrcOp &Op0, const SrcOp &Op1) { in buildSAddo() argument
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