343       const MachineOperand &Op1 = MI->getOperand(1);  in profit()  local
345       int32_t Prof1 = Op1.isImm() ? profitImm(Op1.getImm()) : 0;  in profit()
698   MachineOperand &Op1 = MI->getOperand(1);  in splitImmediate()  local
699   assert(Op0.isReg() && Op1.isImm());  in splitImmediate()
700   uint64_t V = Op1.getImm();  in splitImmediate()
725   MachineOperand &Op1 = MI->getOperand(1);  in splitCombine()  local
735   if (!Op1.isReg()) {  in splitCombine()
737       .add(Op1);  in splitCombine()
740       .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg());  in splitCombine()
755   MachineOperand &Op1 = MI->getOperand(1);  in splitExt()  local
756   assert(Op0.isReg() && Op1.isReg());  in splitExt()
763   unsigned RS = getRegState(Op1);  in splitExt()
766     .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg());  in splitExt()
768     .addReg(Op1.getReg(), RS, Op1.getSubReg())  in splitExt()
777   MachineOperand &Op1 = MI->getOperand(1);  in splitShift()  local
779   assert(Op0.isReg() && Op1.isReg() && Op2.isImm());  in splitShift()
797   unsigned RS = getRegState(Op1);  in splitShift()
806       .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
808       .addReg(Op1.getReg(), RS, HiSR);  in splitShift()
831         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
834         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
837         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)  in splitShift()
843         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)  in splitShift()
849         .addReg(Op1.getReg(), RS, HiSR)  in splitShift()
854         .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR)  in splitShift()
859         .addReg(Op1.getReg(), RS, HiSR)  in splitShift()
865       .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR));  in splitShift()
871         .addReg(Op1.getReg(), RS, HiSR)  in splitShift()
877         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
880         .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR);  in splitShift()
883         .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR))  in splitShift()
888         .addReg(Op1.getReg(), RS, HiSR)  in splitShift()
901   MachineOperand &Op1 = MI->getOperand(1);  in splitAslOr()  local
904   assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm());  in splitAslOr()
917   unsigned RS1 = getRegState(Op1);  in splitAslOr()
941       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)  in splitAslOr()
944       .addReg(Op1.getReg(), RS1, HiSR)  in splitAslOr()
948       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)  in splitAslOr()
958       .addReg(Op1.getReg(), RS1, HiSR)  in splitAslOr()
970       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);  in splitAslOr()
972       .addReg(Op1.getReg(), RS1, HiSR)  in splitAslOr()
981       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);  in splitAslOr()
983       .addReg(Op1.getReg(), RS1, HiSR)  in splitAslOr()