| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFrameLowering.cpp | 303 Register OffsetReg = MRI.createVirtualRegister(PtrRC); in emitPrologue()
304 BuildMI(MBB, InsertPt, DL, TII->get(getOpcConst(MF)), OffsetReg) in emitPrologue()
308 .addReg(OffsetReg); in emitPrologue()
355 Register OffsetReg = MRI.createVirtualRegister(PtrRC); in emitEpilogue()
356 BuildMI(MBB, InsertPt, DL, TII->get(getOpcConst(MF)), OffsetReg) in emitEpilogue()
364 .addReg(OffsetReg); in isSupportedStackID()
295 Register OffsetReg = MRI.createVirtualRegister(PtrRC); emitPrologue() local
347 Register OffsetReg = MRI.createVirtualRegister(PtrRC); emitEpilogue() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.h | 50 unsigned OffsetReg,
56 unsigned OffsetReg,
246 unsigned OffsetReg) const;
254 unsigned OffsetReg) const;
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| H A D | R600InstrInfo.cpp | 1012 Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
1013 if (OffsetReg == R600::INDIRECT_BASE_ADDR) { in expandPostRAPseudo()
1018 OffsetReg); in expandPostRAPseudo()
1026 Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
1027 if (OffsetReg == R600::INDIRECT_BASE_ADDR) { in expandPostRAPseudo()
1033 OffsetReg); in expandPostRAPseudo()
1088 unsigned OffsetReg) const { in buildIndirectWrite()
1089 return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0); in buildIndirectWrite()
1095 unsigned OffsetReg, in buildIndirectWrite() argument
1106 R600::AR_X, OffsetReg); in buildIndirectWrite()
[all …]
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| H A D | AMDGPUCallLowering.cpp | 226 auto OffsetReg = MIRBuilder.buildConstant(S32, Offset); in getStackAddress() local
228 auto AddrReg = MIRBuilder.buildPtrAdd(PtrTy, SPReg, OffsetReg); in getStackAddress()
409 auto OffsetReg = B.buildConstant(LLT::scalar(64), Offset); in lowerParameterPtr() local
411 B.buildPtrAdd(DstReg, KernArgSegmentVReg, OffsetReg); in lowerParameterPtr()
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| H A D | SIRegisterInfo.cpp | 851 Register OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); in materializeFrameBaseRegister() local
857 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg) in materializeFrameBaseRegister()
864 .addReg(OffsetReg, RegState::Kill) in materializeFrameBaseRegister()
870 .addReg(OffsetReg, RegState::Kill) in materializeFrameBaseRegister()
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| H A D | AMDGPUInstructionSelector.cpp | 848 Register OffsetReg = MI.getOperand(2).getReg(); in selectG_SBFX_UBFX() local
863 .addReg(OffsetReg) in selectG_SBFX_UBFX()
4193 if (Register OffsetReg = in selectSmrdOffset() local
4196 *SOffset = OffsetReg; in selectSmrdOffset()
4239 if (Register OffsetReg = matchZeroExtendFromS32(*MRI, GEPI.SgprParts[1])) { in selectSmrdOffset() local
4241 *SOffset = OffsetReg; in selectSmrdOffset()
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| H A D | AMDGPURegisterBankInfo.cpp | 1463 Register OffsetReg = MI.getOperand(FirstOpnd + 1).getReg(); in applyMappingBFE() local
1478 auto ShiftOffset = Signed ? B.buildAShr(S64, SrcReg, OffsetReg) in applyMappingBFE()
1479 : B.buildLShr(S64, SrcReg, OffsetReg); in applyMappingBFE()
1530 auto ClampOffset = B.buildAnd(S32, OffsetReg, OffsetMask); in applyMappingBFE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/ |
| H A D | LanaiAsmParser.cpp | 130 unsigned OffsetReg; member
176 return Mem.OffsetReg; in getMemOffsetReg()
616 Op->Mem.OffsetReg = 0; in MorphToMemImm()
624 unsigned OffsetReg = Op->getReg(); in MorphToMemRegReg() local
628 Op->Mem.OffsetReg = OffsetReg; in MorphToMemRegReg()
640 Op->Mem.OffsetReg = 0; in MorphToMemRegImm()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/GISel/ |
| H A D | M68kCallLowering.cpp | 84 auto OffsetReg = MIRBuilder.buildConstant(SType, Offset); in getStackAddress() local
85 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | Thumb2SizeReduction.cpp | 565 unsigned OffsetReg = 0; in ReduceLoadStore() local
569 OffsetReg = MI->getOperand(2).getReg(); in ReduceLoadStore()
604 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); in ReduceLoadStore()
607 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
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| H A D | ARMCallLowering.cpp | 111 auto OffsetReg = MIRBuilder.buildConstant(s32, Offset); in getStackAddress() local
113 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
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| H A D | Thumb2InstrInfo.cpp | 645 Register OffsetReg = MI.getOperand(FrameRegIdx + 1).getReg(); in rewriteT2FrameIndex() local
646 if (OffsetReg != 0) { in rewriteT2FrameIndex()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | |
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86CallLowering.cpp | 101 auto OffsetReg = MIRBuilder.buildConstant(SType, Offset); in getStackAddress() local
103 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 244 unsigned OffsetReg; member
340 return Mem.OffsetReg; in getMemOffsetReg()
578 Op->Mem.OffsetReg = offsetReg; in MorphToMEMrr()
587 Op->Mem.OffsetReg = Sparc::G0; // always 0 in CreateMEMr()
599 Op->Mem.OffsetReg = 0; in MorphToMEMri()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsCallLowering.cpp | 239 auto OffsetReg = MIRBuilder.buildConstant(s32, Offset); in getStackAddress()
240 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
238 auto OffsetReg = MIRBuilder.buildConstant(s32, Offset); getStackAddress() local
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| H A D | MipsSEInstrInfo.cpp | 865 Register OffsetReg = I->getOperand(0).getReg(); in expandEhReturn() local
879 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg); in expandEhReturn()
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| H A D | MipsISelLowering.cpp | 2582 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1; in lowerEH_RETURN() local
2584 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); in lowerEH_RETURN()
2587 DAG.getRegister(OffsetReg, Ty), in lowerEH_RETURN()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVCallLowering.cpp | 80 auto OffsetReg = MIRBuilder.buildConstant(sXLen, Offset); in getStackAddress() local
82 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonOptAddrMode.cpp | 170 Register OffsetReg = MI.getOperand(2).getReg(); in canRemoveAddasl() local
175 if (OffsetReg == RR.Reg) { in canRemoveAddasl()
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| H A D | HexagonISelLowering.cpp | 3325 unsigned OffsetReg = Hexagon::R28; in LowerEH_RETURN() local
3331 Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset); in LowerEH_RETURN()
3334 // MF.getRegInfo().addLiveOut(OffsetReg); in LowerEH_RETURN()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64CallLowering.cpp | 273 auto OffsetReg = MIRBuilder.buildConstant(s64, Offset); in getStackAddress() local
275 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
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| H A D | AArch64InstructionSelector.cpp | 6769 Register OffsetReg = DefMI->getOperand(2).getReg(); in selectPtrAuthGlobalValue() local
6770 if (!MRI.hasOneDef(OffsetReg)) in selectPtrAuthGlobalValue()
6772 const MachineInstr &OffsetMI = *MRI.def_instr_begin(OffsetReg); in selectPtrAuthGlobalValue()
7102 Register OffsetReg = OffsetInst->getOperand(1).getReg(); in selectExtendedSHL() local
7112 std::swap(OffsetReg, ConstantReg); in selectExtendedSHL()
7145 MachineInstr *ExtInst = getDefIgnoringCopies(OffsetReg, MRI); in selectExtendedSHL()
7154 OffsetReg = ExtInst->getOperand(1).getReg(); in selectExtendedSHL()
7159 OffsetReg = moveScalarRegClass(OffsetReg, AArch64::GPR32RegClass, MIB); in selectExtendedSHL()
7165 [=](MachineInstrBuilder &MIB) { MIB.addUse(OffsetReg); }, in selectExtendedSHL()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 2899 Register OffsetReg = AddrI.getOperand(2).getReg(); in canFoldIntoAddrMode() local
2900 if (!OffsetReg.isVirtual() || !MRI.hasOneNonDBGUse(OffsetReg)) in canFoldIntoAddrMode()
2903 const MachineInstr &DefMI = *MRI.getVRegDef(OffsetReg); in canFoldIntoAddrMode()
3466 Register OffsetReg = AM.ScaledReg; in emitLdStWithAddr() local
3467 const TargetRegisterClass *RC = MRI.getRegClass(OffsetReg); in emitLdStWithAddr()
3469 OffsetReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass); in emitLdStWithAddr()
3470 BuildMI(MBB, MemI, DL, get(TargetOpcode::COPY), OffsetReg) in emitLdStWithAddr()
3477 .addReg(OffsetReg) in emitLdStWithAddr()
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| H A D | AArch64FastISel.cpp | 97 unsigned OffsetReg = 0; member in __anon53fc71c20111::AArch64FastISel::Address
123 OffsetReg = Reg; in setOffsetReg()
127 return OffsetReg; in getOffsetReg()
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