| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFrameLowering.cpp | 301 Register OffsetReg = MRI.createVirtualRegister(PtrRC); in emitPrologue() local
302 BuildMI(MBB, InsertPt, DL, TII->get(getOpcConst(MF)), OffsetReg) in emitPrologue()
306 .addReg(OffsetReg); in emitPrologue()
353 Register OffsetReg = MRI.createVirtualRegister(PtrRC); in emitEpilogue() local
354 BuildMI(MBB, InsertPt, DL, TII->get(getOpcConst(MF)), OffsetReg) in emitEpilogue()
362 .addReg(OffsetReg); in emitEpilogue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.h | 51 unsigned OffsetReg,
57 unsigned OffsetReg,
248 unsigned OffsetReg) const;
256 unsigned OffsetReg) const;
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| H A D | R600InstrInfo.cpp | 1002 Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
1003 if (OffsetReg == R600::INDIRECT_BASE_ADDR) { in expandPostRAPseudo()
1008 OffsetReg); in expandPostRAPseudo()
1016 Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
1017 if (OffsetReg == R600::INDIRECT_BASE_ADDR) { in expandPostRAPseudo()
1023 OffsetReg); in expandPostRAPseudo()
1079 unsigned OffsetReg) const { in buildIndirectWrite()
1080 return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0); in buildIndirectWrite()
1086 unsigned OffsetReg, in buildIndirectWrite() argument
1097 R600::AR_X, OffsetReg); in buildIndirectWrite()
[all …]
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| H A D | AMDGPUCallLowering.cpp | 225 auto OffsetReg = MIRBuilder.buildConstant(S32, Offset); in getStackAddress() local
227 auto AddrReg = MIRBuilder.buildPtrAdd(PtrTy, SPReg, OffsetReg); in getStackAddress()
401 auto OffsetReg = B.buildConstant(LLT::scalar(64), Offset); in lowerParameterPtr() local
403 B.buildPtrAdd(DstReg, KernArgSegmentVReg, OffsetReg); in lowerParameterPtr()
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| H A D | SIRegisterInfo.cpp | 982 Register OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); in materializeFrameBaseRegister() local
988 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg) in materializeFrameBaseRegister()
996 .addReg(OffsetReg, RegState::Kill) in materializeFrameBaseRegister()
1003 .addReg(OffsetReg, RegState::Kill) in materializeFrameBaseRegister()
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| H A D | AMDGPUInstructionSelector.cpp | 946 Register OffsetReg = MI.getOperand(2).getReg(); in selectG_SBFX_UBFX() local
961 .addReg(OffsetReg) in selectG_SBFX_UBFX()
5227 if (Register OffsetReg = in selectSmrdOffset() local
5230 *SOffset = OffsetReg; in selectSmrdOffset()
5273 if (Register OffsetReg = matchZeroExtendFromS32(*MRI, GEPI.SgprParts[1])) { in selectSmrdOffset() local
5275 *SOffset = OffsetReg; in selectSmrdOffset()
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| H A D | AMDGPURegisterBankInfo.cpp | 1491 Register OffsetReg = MI.getOperand(FirstOpnd + 1).getReg(); in applyMappingBFE() local
1506 auto ShiftOffset = Signed ? B.buildAShr(S64, SrcReg, OffsetReg) in applyMappingBFE()
1507 : B.buildLShr(S64, SrcReg, OffsetReg); in applyMappingBFE()
1558 auto ClampOffset = B.buildAnd(S32, OffsetReg, OffsetMask); in applyMappingBFE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/ |
| H A D | LanaiAsmParser.cpp | 129 MCRegister OffsetReg; member
175 return Mem.OffsetReg; in getMemOffsetReg()
615 Op->Mem.OffsetReg = 0; in MorphToMemImm()
623 MCRegister OffsetReg = Op->getReg(); in MorphToMemRegReg() local
627 Op->Mem.OffsetReg = OffsetReg; in MorphToMemRegReg()
639 Op->Mem.OffsetReg = 0; in MorphToMemRegImm()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/GISel/ |
| H A D | M68kCallLowering.cpp | 84 auto OffsetReg = MIRBuilder.buildConstant(SType, Offset); in getStackAddress() local
85 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | Thumb2SizeReduction.cpp | 562 unsigned OffsetReg = 0; in ReduceLoadStore() local
566 OffsetReg = MI->getOperand(2).getReg(); in ReduceLoadStore()
601 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); in ReduceLoadStore()
604 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
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| H A D | ARMCallLowering.cpp | 111 auto OffsetReg = MIRBuilder.buildConstant(s32, Offset); in getStackAddress() local
113 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
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| H A D | Thumb2InstrInfo.cpp | 647 Register OffsetReg = MI.getOperand(FrameRegIdx + 1).getReg(); in rewriteT2FrameIndex() local
648 if (OffsetReg != 0) { in rewriteT2FrameIndex()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | |
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86CallLowering.cpp | 100 auto OffsetReg = MIRBuilder.buildConstant(SType, Offset); in getStackAddress() local
102 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonOptAddrMode.cpp | 175 Register OffsetReg = MI.getOperand(2).getReg(); in canRemoveAddasl() local
180 if (OffsetReg == RR.Reg) { in canRemoveAddasl()
219 if (!UseMI.getParent()->isLiveIn(OffsetReg) && in canRemoveAddasl()
221 LLVM_DEBUG(dbgs() << " The offset reg " << printReg(OffsetReg, TRI) in canRemoveAddasl()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 248 unsigned OffsetReg; member
344 return Mem.OffsetReg; in getMemOffsetReg()
600 Op->Mem.OffsetReg = offsetReg; in MorphToMEMrr()
609 Op->Mem.OffsetReg = Sparc::G0; // always 0 in CreateMEMr()
621 Op->Mem.OffsetReg = 0; in MorphToMEMri()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 398 MCRegister OffsetReg; member
1077 << RegName(RegReg.OffsetReg); in print()
1163 createRegReg(MCRegister BaseReg, MCRegister OffsetReg, SMLoc S) { in createRegReg()
1166 Op->RegReg.OffsetReg = OffsetReg; in createRegReg()
1255 Inst.addOperand(MCOperand::createReg(RegReg.OffsetReg)); in addRegRegOperands()
2713 MCRegister OffsetReg = matchRegisterNameHelper(OffsetRegName); in parseRegReg() local
2714 if (!OffsetReg || in parseRegReg()
2715 !RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(OffsetReg)) in parseRegReg()
2735 Operands.push_back(RISCVOperand::createRegReg(BaseReg, OffsetReg, S)); in parseRegReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsCallLowering.cpp | 239 auto OffsetReg = MIRBuilder.buildConstant(s32, Offset); in getStackAddress() local
240 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
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| H A D | MipsSEInstrInfo.cpp | 865 Register OffsetReg = I->getOperand(0).getReg(); in expandEhReturn() local
879 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg); in expandEhReturn()
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| H A D | MipsISelLowering.cpp | 2734 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1; in lowerEH_RETURN() local
2736 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); in lowerEH_RETURN()
2739 DAG.getRegister(OffsetReg, Ty), in lowerEH_RETURN()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVCallLowering.cpp | 72 auto OffsetReg = MIRBuilder.buildConstant(sXLen, Offset); in getStackAddress() local
74 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64CallLowering.cpp | 275 auto OffsetReg = MIRBuilder.buildConstant(s64, Offset); in getStackAddress() local
277 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
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| H A D | AArch64InstructionSelector.cpp | 6942 Register OffsetReg = DefMI->getOperand(2).getReg(); in selectPtrAuthGlobalValue() local
6943 if (!MRI.hasOneDef(OffsetReg)) in selectPtrAuthGlobalValue()
6945 const MachineInstr &OffsetMI = *MRI.def_instr_begin(OffsetReg); in selectPtrAuthGlobalValue()
7275 Register OffsetReg = OffsetInst->getOperand(1).getReg(); in selectExtendedSHL() local
7285 std::swap(OffsetReg, ConstantReg); in selectExtendedSHL()
7318 MachineInstr *ExtInst = getDefIgnoringCopies(OffsetReg, MRI); in selectExtendedSHL()
7327 OffsetReg = ExtInst->getOperand(1).getReg(); in selectExtendedSHL()
7332 OffsetReg = moveScalarRegClass(OffsetReg, AArch64::GPR32RegClass, MIB); in selectExtendedSHL()
7338 [=](MachineInstrBuilder &MIB) { MIB.addUse(OffsetReg); }, in selectExtendedSHL()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 3179 Register OffsetReg = AddrI.getOperand(2).getReg(); in canFoldIntoAddrMode() local
3180 if (!OffsetReg.isVirtual() || !MRI.hasOneNonDBGUse(OffsetReg)) in canFoldIntoAddrMode()
3183 const MachineInstr &DefMI = *MRI.getVRegDef(OffsetReg); in canFoldIntoAddrMode()
3748 Register OffsetReg = AM.ScaledReg; in emitLdStWithAddr() local
3749 const TargetRegisterClass *RC = MRI.getRegClass(OffsetReg); in emitLdStWithAddr()
3751 OffsetReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass); in emitLdStWithAddr()
3752 BuildMI(MBB, MemI, DL, get(TargetOpcode::COPY), OffsetReg) in emitLdStWithAddr()
3759 .addReg(OffsetReg) in emitLdStWithAddr()
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| H A D | AArch64FastISel.cpp | 96 Register OffsetReg; member in __anon53fc71c20111::AArch64FastISel::Address
121 void setOffsetReg(Register Reg) { OffsetReg = Reg; } in setOffsetReg()
123 Register getOffsetReg() const { return OffsetReg; } in getOffsetReg()
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