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Searched refs:NewVT (Results 1 – 25 of 29) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1197 MVT NewVT = MVT::getVectorVT(EltTy, EC); in getVectorTypeBreakdownMVT() local
1198 if (!TLI->isTypeLegal(NewVT)) in getVectorTypeBreakdownMVT()
1199 NewVT = EltTy; in getVectorTypeBreakdownMVT()
1200 IntermediateVT = NewVT; in getVectorTypeBreakdownMVT()
1202 unsigned LaneSizeInBits = NewVT.getScalarSizeInBits(); in getVectorTypeBreakdownMVT()
1207 MVT DestVT = TLI->getRegisterType(NewVT); in getVectorTypeBreakdownMVT()
1209 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdownMVT()
1685 EVT NewVT = EVT::getVectorVT(Context, EltTy, EltCnt); in getVectorTypeBreakdown() local
1686 if (!isTypeLegal(NewVT)) in getVectorTypeBreakdown()
1687 NewVT = EltTy; in getVectorTypeBreakdown()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp218 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT); in ExpandRes_EXTRACT_VECTOR_ELT() local
231 EVT::getVectorVT(*DAG.getContext(), NewVT, OldEltCount * 2), OldVec); in ExpandRes_EXTRACT_VECTOR_ELT()
237 Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
241 Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
372 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT); in ExpandOp_BUILD_VECTOR() local
401 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NewElts.size()); in ExpandOp_BUILD_VECTOR()
H A DLegalizeVectorTypes.cpp403 EVT NewVT = N->getValueType(0).getVectorElementType(); in ScalarizeVecRes_BITCAST() local
405 NewVT, Op); in ScalarizeVecRes_BITCAST()
2769 EVT NewVT = Inputs[0].getValueType(); in SplitVecRes_VECTOR_SHUFFLE() local
2770 unsigned NewElts = NewVT.getVectorNumElements(); in SplitVecRes_VECTOR_SHUFFLE()
2778 auto &&BuildVector = [NewElts, &DAG = DAG, NewVT, &DL](SDValue &Input1, in SplitVecRes_VECTOR_SHUFFLE()
2784 EVT EltVT = NewVT.getVectorElementType(); in SplitVecRes_VECTOR_SHUFFLE()
2798 return DAG.getBuildVector(NewVT, DL, Ops); in SplitVecRes_VECTOR_SHUFFLE()
2806 auto &&TryPeekThroughShufflesInputs = [&Inputs, &NewVT, this, NewElts, in SplitVecRes_VECTOR_SHUFFLE()
2925 if (Shuffle->getOperand(0).getValueType() != NewVT) in SplitVecRes_VECTOR_SHUFFLE()
3081 [&Output, &DAG = DAG, NewVT]() { Output = DAG.getUNDEF(NewVT); }, in SplitVecRes_VECTOR_SHUFFLE()
[all …]
H A DDAGCombiner.cpp5445 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); in visitMULHS() local
5446 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHS()
5447 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); in visitMULHS()
5448 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); in visitMULHS()
5449 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); in visitMULHS()
5450 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHS()
5451 DAG.getShiftAmountConstant(SimpleSize, NewVT, DL)); in visitMULHS()
5515 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); in visitMULHU() local
5516 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHU()
5517 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); in visitMULHU()
[all …]
H A DTargetLowering.cpp251 EVT NewVT = VT; in findOptimalMemOpLowering() local
256 NewVT = (VT.getSizeInBits() > 64) ? MVT::i64 : MVT::i32; in findOptimalMemOpLowering()
257 if (isOperationLegalOrCustom(ISD::STORE, NewVT) && in findOptimalMemOpLowering()
258 isSafeMemOpType(NewVT.getSimpleVT())) in findOptimalMemOpLowering()
260 else if (NewVT == MVT::i64 && in findOptimalMemOpLowering()
264 NewVT = MVT::f64; in findOptimalMemOpLowering()
271 NewVT = (MVT::SimpleValueType)(NewVT.getSimpleVT().SimpleTy - 1); in findOptimalMemOpLowering()
272 if (NewVT == MVT::i8) in findOptimalMemOpLowering()
274 } while (!isSafeMemOpType(NewVT.getSimpleVT())); in findOptimalMemOpLowering()
276 NewVTSize = NewVT.getSizeInBits() / 8; in findOptimalMemOpLowering()
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H A DLegalizeDAG.cpp3566 EVT NewVT = in ExpandNode() local
3569 assert(NewVT.bitsEq(VT)); in ExpandNode()
3572 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0); in ExpandNode()
3573 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1); in ExpandNode()
3577 NewVT.getVectorNumElements()/VT.getVectorNumElements(); in ExpandNode()
3593 VT = NewVT; in ExpandNode()
H A DLegalizeIntegerTypes.cpp823 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); in PromoteIntRes_VP_CttzElements() local
824 return DAG.getNode(N->getOpcode(), DL, NewVT, N->ops()); in PromoteIntRes_VP_CttzElements()
3443 EVT NewVT = getSetCCResultType(LHS.getValueType()); in ExpandIntRes_SETCC() local
3446 SDValue Res = DAG.getNode(ISD::SETCC, DL, NewVT, LHS, RHS, N->getOperand(2)); in ExpandIntRes_SETCC()
3448 Res = DAG.getBoolExtOrTrunc(Res, DL, N->getValueType(0), NewVT); in ExpandIntRes_SETCC()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.h140 shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT, in shouldReduceLoadWidth() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp451 MVT NewVT = TLI.getRegisterTypeForCallingConv(Ctx, CC, SplitEVTs[i]); in lowerReturn() local
452 if (EVT(NewVT) != SplitEVTs[i]) { in lowerReturn()
459 LLT NewLLT(NewVT); in lowerReturn()
461 CurArgInfo.Ty = EVT(NewVT).getTypeForEVT(Ctx); in lowerReturn()
464 if (NewVT.isVector()) { in lowerReturn()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp683 MVT NewVT = TLI->getRegisterTypeForCallingConv(Ctx, CallConv, CurVT); in determineAssignments() local
692 if (Assigner.assignArg(i, CurVT, NewVT, NewVT, CCValAssign::Full, Args[i], in determineAssignments()
723 if (Assigner.assignArg(i, CurVT, NewVT, NewVT, CCValAssign::Full, Args[i], in determineAssignments()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstCombineIntrinsic.cpp1885 Type *NewVT = MaskLen == 1 ? EltTy : FixedVectorType::get(EltTy, MaskLen); in simplifyAMDGCNLaneIntrinsicDemanded() local
1889 if (!isTypeLegal(NewVT)) in simplifyAMDGCNLaneIntrinsicDemanded()
1901 Intrinsic::getOrInsertDeclaration(M, II.getIntrinsicID(), {NewVT}); in simplifyAMDGCNLaneIntrinsicDemanded()
H A DAMDGPUISelLowering.cpp832 SDNode *N, ISD::LoadExtType ExtTy, EVT NewVT, in shouldReduceLoadWidth() argument
835 if (!TargetLoweringBase::shouldReduceLoadWidth(N, ExtTy, NewVT, ByteOffset)) in shouldReduceLoadWidth()
838 unsigned NewSize = NewVT.getStoreSizeInBits(); in shouldReduceLoadWidth()
1586 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, in LowerCONCAT_VECTORS() local
1588 SDValue BV = DAG.getBuildVector(NewVT, SL, Args); in LowerCONCAT_VECTORS()
1614 EVT NewVT = NumElt == 2 in LowerEXTRACT_SUBVECTOR() local
1623 Tmp = DAG.getBuildVector(NewVT, SL, Args); in LowerEXTRACT_SUBVECTOR()
3905 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT); in performLoadCombine() local
3908 = DAG.getLoad(NewVT, SL, LN->getChain(), in performLoadCombine()
3956 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT); in performStoreCombine() local
[all …]
H A DR600ISelLowering.cpp1699 EVT NewVT = MVT::v4i32; in constBufferLoad() local
1702 NewVT = VT; in constBufferLoad()
1705 SDValue Result = DAG.getBuildVector(NewVT, DL, ArrayRef(Slots, NumElements)); in constBufferLoad()
H A DSIISelLowering.cpp6787 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT); in ReplaceNodeResults() local
6788 SDValue LHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(1)); in ReplaceNodeResults()
6789 SDValue RHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(2)); in ReplaceNodeResults()
6791 EVT SelectVT = NewVT; in ReplaceNodeResults()
6792 if (NewVT.bitsLT(MVT::i32)) { in ReplaceNodeResults()
6801 if (NewVT != SelectVT) in ReplaceNodeResults()
6802 NewSelect = DAG.getNode(ISD::TRUNCATE, SL, NewVT, NewSelect); in ReplaceNodeResults()
8716 EVT NewVT = NumVDataDwords > 1 ? EVT::getVectorVT(*DAG.getContext(), in lowerImage() local
8720 ResultTypes[0] = NewVT; in lowerImage()
14271 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VecVT); in performExtractVectorEltCombine() local
[all …]
H A DAMDGPUISelDAGToDAG.cpp794 MVT NewVT = Opc == AMDGPUISD::CVT_PKRTZ_F16_F32 ? MVT::v2f16 : MVT::v2i16; in Select() local
795 N = CurDAG->MorphNodeTo(N, N->getOpcode(), CurDAG->getVTList(NewVT), in Select()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp5672 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2); in tryWidenMaskForShuffle() local
5673 if (!DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) in tryWidenMaskForShuffle()
5675 V0 = DAG.getBitcast(NewVT, V0); in tryWidenMaskForShuffle()
5676 V1 = DAG.getBitcast(NewVT, V1); in tryWidenMaskForShuffle()
5677 return DAG.getBitcast(VT, DAG.getVectorShuffle(NewVT, DL, V0, V1, NewMask)); in tryWidenMaskForShuffle()
5884 EVT NewVT = VT.getDoubleNumVectorElementsVT(); in lowerVECTOR_SHUFFLE() local
5885 Src = DAG.getExtractSubvector(DL, NewVT, Src, 0); in lowerVECTOR_SHUFFLE()
5887 lowerVZIP(Opc, Src, DAG.getUNDEF(NewVT), DL, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
6114 MVT NewVT = MVT::getVectorVT(VT.getVectorElementType(), NewNumElts); in lowerVECTOR_SHUFFLE() local
6115 V1 = DAG.getExtractSubvector(DL, NewVT, V1, 0); in lowerVECTOR_SHUFFLE()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h361 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT,
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp880 EVT NewVT = ResTy.is128BitVector() ? MVT::v2i64 : MVT::v4i64; in lowerBITREVERSE() local
882 unsigned int NewEltNum = NewVT.getVectorNumElements(); in lowerBITREVERSE()
884 SDValue NewSrc = DAG.getNode(ISD::BITCAST, DL, NewVT, Src); in lowerBITREVERSE()
896 DAG.getNode(ISD::BITCAST, DL, ResTy, DAG.getBuildVector(NewVT, DL, Ops)); in lowerBITREVERSE()
936 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2); in widenShuffleMask() local
937 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) { in widenShuffleMask()
938 SDValue NewV1 = DAG.getBitcast(NewVT, V1); in widenShuffleMask()
939 SDValue NewV2 = DAG.getBitcast(NewVT, V2); in widenShuffleMask()
941 VT, DAG.getVectorShuffle(NewVT, DL, NewV1, NewV2, NewMask)); in widenShuffleMask()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h193 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT,
H A DAArch64ISelLowering.cpp4509 EVT NewVT = VT.changeElementType(MVT::f32); in LowerVectorFP_TO_INT() local
4512 SDValue Ext = DAG.getNode(ISD::STRICT_FP_EXTEND, DL, {NewVT, MVT::Other}, in LowerVectorFP_TO_INT()
4519 DAG.getNode(ISD::FP_EXTEND, DL, NewVT, Op.getOperand(0))); in LowerVectorFP_TO_INT()
6365 EVT NewVT = getTypeToTransformTo(*DAG.getContext(), VT); in LowerINTRINSIC_WO_CHAIN() local
6366 SDValue Mask = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, CttzOp); in LowerINTRINSIC_WO_CHAIN()
13890 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2); in tryWidenMaskForShuffle() local
13891 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) { in tryWidenMaskForShuffle()
13892 V0 = DAG.getBitcast(NewVT, V0); in tryWidenMaskForShuffle()
13893 V1 = DAG.getBitcast(NewVT, V1); in tryWidenMaskForShuffle()
13895 DAG.getVectorShuffle(NewVT, DL, V0, V1, NewMask)); in tryWidenMaskForShuffle()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h1515 shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT,
H A DX86ISelLowering.cpp3245 SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT, in shouldReduceLoadWidth() argument
3303 return (ByteOffset.value_or(0) > 0) || NewVT.isScalarInteger(); in shouldReduceLoadWidth()
8247 MVT NewVT = V0_LO.getSimpleValueType(); in ExpandHorizontalBinOp() local
8249 SDValue LO = DAG.getUNDEF(NewVT); in ExpandHorizontalBinOp()
8250 SDValue HI = DAG.getUNDEF(NewVT); in ExpandHorizontalBinOp()
8255 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI); in ExpandHorizontalBinOp()
8257 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI); in ExpandHorizontalBinOp()
8261 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO); in ExpandHorizontalBinOp()
8264 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI); in ExpandHorizontalBinOp()
12680 MVT NewVT = V.getSimpleValueType(); in getScalarValueForVectorElement() local
[all …]
/freebsd/contrib/llvm-project/clang/lib/AST/
H A DDecl.cpp2757 auto *NewVT = VarTemplate->getInstantiatedFromMemberTemplate(); in getTemplateInstantiationPattern() local
2758 if (!NewVT) in getTemplateInstantiationPattern()
2760 VarTemplate = NewVT; in getTemplateInstantiationPattern()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineCalls.cpp3109 VectorType *NewVT = cast<VectorType>(II->getType()); in visitCallInst() local
3112 Value *V0 = Builder.CreateIntCast(CV0, NewVT, /*isSigned=*/!Zext); in visitCallInst()
3113 Value *V1 = Builder.CreateIntCast(CV1, NewVT, /*isSigned=*/!Zext); in visitCallInst()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h1855 SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT,
1859 if (NewVT.isVector() && !SDValue(Load, 0).hasOneUse())

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