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Searched refs:NewVT (Results 1 – 25 of 28) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1098 MVT NewVT = MVT::getVectorVT(EltTy, EC); in getVectorTypeBreakdownMVT() local
1099 if (!TLI->isTypeLegal(NewVT)) in getVectorTypeBreakdownMVT()
1100 NewVT = EltTy; in getVectorTypeBreakdownMVT()
1101 IntermediateVT = NewVT; in getVectorTypeBreakdownMVT()
1103 unsigned LaneSizeInBits = NewVT.getScalarSizeInBits(); in getVectorTypeBreakdownMVT()
1108 MVT DestVT = TLI->getRegisterType(NewVT); in getVectorTypeBreakdownMVT()
1110 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdownMVT()
1586 EVT NewVT = EVT::getVectorVT(Context, EltTy, EltCnt); in getVectorTypeBreakdown() local
1587 if (!isTypeLegal(NewVT)) in getVectorTypeBreakdown()
1588 NewVT = EltTy; in getVectorTypeBreakdown()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp218 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT); in ExpandRes_EXTRACT_VECTOR_ELT() local
231 EVT::getVectorVT(*DAG.getContext(), NewVT, OldEltCount * 2), OldVec); in ExpandRes_EXTRACT_VECTOR_ELT()
237 Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
241 Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
373 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT); in ExpandOp_BUILD_VECTOR() local
393 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NewElts.size()); in ExpandOp_BUILD_VECTOR()
H A DLegalizeVectorTypes.cpp394 EVT NewVT = N->getValueType(0).getVectorElementType();
396 NewVT, Op); in ScalarizeVecRes_BUILD_VECTOR()
2634 EVT NewVT = Inputs[0].getValueType(); in SplitVecRes_VECTOR_SHUFFLE()
2635 unsigned NewElts = NewVT.getVectorNumElements(); in SplitVecRes_VECTOR_SHUFFLE()
2643 auto &&BuildVector = [NewElts, &DAG = DAG, NewVT, &DL](SDValue &Input1, in SplitVecRes_VECTOR_SHUFFLE()
2649 EVT EltVT = NewVT.getVectorElementType(); in SplitVecRes_VECTOR_SHUFFLE()
2663 return DAG.getBuildVector(NewVT, DL, Ops); in SplitVecRes_VECTOR_SHUFFLE()
2671 auto &&TryPeekThroughShufflesInputs = [&Inputs, &NewVT, this, NewElts, in SplitVecRes_VECTOR_SHUFFLE()
2790 if (Shuffle->getOperand(0).getValueType() != NewVT) in SplitVecRes_VECTOR_SHUFFLE()
2946 [&Output, &DAG = DAG, NewVT]() { Outpu in SplitVecRes_VECTOR_SHUFFLE()
390 EVT NewVT = N->getValueType(0).getVectorElementType(); ScalarizeVecRes_BITCAST() local
2630 EVT NewVT = Inputs[0].getValueType(); SplitVecRes_VECTOR_SHUFFLE() local
6716 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts); WidenVecOp_BITCAST() local
6735 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NewNumElts); WidenVecOp_BITCAST() local
7431 std::optional<EVT> NewVT = FirstVT; GenWidenVectorLoads() local
7654 std::optional<EVT> NewVT = GenWidenVectorStores() local
7668 EVT NewVT = Pair.first; GenWidenVectorStores() local
[all...]
H A DDAGCombiner.cpp5101 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); in visitMULHS() local
5102 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHS()
5103 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); in visitMULHS()
5104 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); in visitMULHS()
5105 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); in visitMULHS()
5106 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHS()
5107 DAG.getShiftAmountConstant(SimpleSize, NewVT, DL)); in visitMULHS()
5171 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); in visitMULHU() local
5172 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHU()
5173 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); in visitMULHU()
[all …]
H A DTargetLowering.cpp237 EVT NewVT = VT; in findOptimalMemOpLowering() local
242 NewVT = (VT.getSizeInBits() > 64) ? MVT::i64 : MVT::i32; in findOptimalMemOpLowering()
243 if (isOperationLegalOrCustom(ISD::STORE, NewVT) && in findOptimalMemOpLowering()
244 isSafeMemOpType(NewVT.getSimpleVT())) in findOptimalMemOpLowering()
246 else if (NewVT == MVT::i64 && in findOptimalMemOpLowering()
250 NewVT = MVT::f64; in findOptimalMemOpLowering()
257 NewVT = (MVT::SimpleValueType)(NewVT.getSimpleVT().SimpleTy - 1); in findOptimalMemOpLowering()
258 if (NewVT == MVT::i8) in findOptimalMemOpLowering()
260 } while (!isSafeMemOpType(NewVT.getSimpleVT())); in findOptimalMemOpLowering()
262 NewVTSize = NewVT.getSizeInBits() / 8; in findOptimalMemOpLowering()
[all …]
H A DLegalizeDAG.cpp3494 EVT NewVT = in ExpandNode() local
3497 assert(NewVT.bitsEq(VT)); in ExpandNode()
3500 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0); in ExpandNode()
3501 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1); in ExpandNode()
3505 NewVT.getVectorNumElements()/VT.getVectorNumElements(); in ExpandNode()
3521 VT = NewVT; in ExpandNode()
H A DSelectionDAGBuilder.cpp8051 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), NewEltTy, in visitIntrinsicCall() local
8057 SDValue StepVec = DAG.getStepVector(DL, NewVT); in visitIntrinsicCall()
8058 SDValue SplatVL = DAG.getSplat(NewVT, DL, VL); in visitIntrinsicCall()
8059 SDValue StepVL = DAG.getNode(ISD::SUB, DL, NewVT, SplatVL, StepVec); in visitIntrinsicCall()
8060 SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, Op); in visitIntrinsicCall()
8061 SDValue And = DAG.getNode(ISD::AND, DL, NewVT, StepVL, Ext); in visitIntrinsicCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.h137 EVT NewVT) const override { in shouldReduceLoadWidth() argument
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp684 MVT NewVT = TLI->getRegisterTypeForCallingConv(Ctx, CallConv, CurVT); in determineAssignments() local
693 if (Assigner.assignArg(i, CurVT, NewVT, NewVT, CCValAssign::Full, Args[i], in determineAssignments()
724 if (Assigner.assignArg(i, CurVT, NewVT, NewVT, CCValAssign::Full, Args[i], in determineAssignments()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp402 MVT NewVT = TLI.getRegisterTypeForCallingConv(Ctx, CC, SplitEVTs[i]); in lowerReturn() local
403 if (EVT(NewVT) != SplitEVTs[i]) { in lowerReturn()
410 LLT NewLLT(NewVT); in lowerReturn()
412 CurArgInfo.Ty = EVT(NewVT).getTypeForEVT(Ctx); in lowerReturn()
415 if (NewVT.isVector()) { in lowerReturn()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp818 EVT NewVT) const { in shouldReduceLoadWidth()
820 if (!TargetLoweringBase::shouldReduceLoadWidth(N, ExtTy, NewVT)) in shouldReduceLoadWidth()
823 unsigned NewSize = NewVT.getStoreSizeInBits(); in shouldReduceLoadWidth()
1529 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, in LowerCONCAT_VECTORS() local
1531 SDValue BV = DAG.getBuildVector(NewVT, SL, Args); in LowerCONCAT_VECTORS()
1557 EVT NewVT = NumElt == 2 in LowerEXTRACT_SUBVECTOR() local
1566 Tmp = DAG.getBuildVector(NewVT, SL, Args); in LowerEXTRACT_SUBVECTOR()
3837 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT); in performLoadCombine() local
3840 = DAG.getLoad(NewVT, SL, LN->getChain(), in performLoadCombine()
3888 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT); in performStoreCombine() local
[all …]
H A DR600ISelLowering.cpp1694 EVT NewVT = MVT::v4i32; in constBufferLoad() local
1697 NewVT = VT; in constBufferLoad()
1700 SDValue Result = DAG.getBuildVector(NewVT, DL, ArrayRef(Slots, NumElements)); in constBufferLoad()
H A DSIISelLowering.cpp6418 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT); in ReplaceNodeResults() local
6419 SDValue LHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(1)); in ReplaceNodeResults()
6420 SDValue RHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(2)); in ReplaceNodeResults()
6422 EVT SelectVT = NewVT; in ReplaceNodeResults()
6423 if (NewVT.bitsLT(MVT::i32)) { in ReplaceNodeResults()
6432 if (NewVT != SelectVT) in ReplaceNodeResults()
6433 NewSelect = DAG.getNode(ISD::TRUNCATE, SL, NewVT, NewSelect); in ReplaceNodeResults()
8153 EVT NewVT = NumVDataDwords > 1 ? in lowerImage() local
8157 ResultTypes[0] = NewVT; in lowerImage()
13458 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VecVT); in performExtractVectorEltCombine() local
[all …]
H A DAMDGPUISelDAGToDAG.cpp678 MVT NewVT = Opc == AMDGPUISD::CVT_PKRTZ_F16_F32 ? MVT::v2f16 : MVT::v2i16; in Select() local
679 N = CurDAG->MorphNodeTo(N, N->getOpcode(), CurDAG->getVTList(NewVT), in Select()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h346 EVT NewVT) const override;
H A DHexagonISelLowering.cpp3840 ISD::LoadExtType ExtTy, EVT NewVT) const { in shouldReduceLoadWidth()
3842 if (!TargetLoweringBase::shouldReduceLoadWidth(Load, ExtTy, NewVT)) in shouldReduceLoadWidth()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp4391 MVT NewVT = MVT::getVectorVT(MVT::f32, NumElts); in LowerVectorFP_TO_INT() local
4394 SDValue Ext = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {NewVT, MVT::Other}, in LowerVectorFP_TO_INT()
4401 DAG.getNode(ISD::FP_EXTEND, dl, NewVT, Op.getOperand(0))); in LowerVectorFP_TO_INT()
4978 EVT NewVT = getExtensionTo64Bits(OrigTy); in addRequiredExtensionForVectorMULL() local
4980 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N); in addRequiredExtensionForVectorMULL()
6073 EVT NewVT = getTypeToTransformTo(*DAG.getContext(), VT); in LowerINTRINSIC_WO_CHAIN() local
6074 SDValue Mask = DAG.getNode(ISD::SIGN_EXTEND, dl, NewVT, CttzOp); in LowerINTRINSIC_WO_CHAIN()
13059 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2); in tryWidenMaskForShuffle() local
13060 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) { in tryWidenMaskForShuffle()
13061 V0 = DAG.getBitcast(NewVT, V0); in tryWidenMaskForShuffle()
[all …]
H A DAArch64ISelLowering.h676 EVT NewVT) const override;
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h1429 EVT NewVT) const override;
H A DX86ISelLowering.cpp3101 EVT NewVT) const { in shouldReduceLoadWidth()
7883 MVT NewVT = V0_LO.getSimpleValueType(); in ExpandHorizontalBinOp() local
7885 SDValue LO = DAG.getUNDEF(NewVT); in ExpandHorizontalBinOp()
7886 SDValue HI = DAG.getUNDEF(NewVT); in ExpandHorizontalBinOp()
7891 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI); in ExpandHorizontalBinOp()
7893 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI); in ExpandHorizontalBinOp()
7897 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO); in ExpandHorizontalBinOp()
7900 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI); in ExpandHorizontalBinOp()
12181 MVT NewVT = V.getSimpleValueType(); in getScalarValueForVectorElement() local
12182 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits()) in getScalarValueForVectorElement()
[all …]
/freebsd/contrib/llvm-project/clang/lib/AST/
H A DDecl.cpp2727 auto *NewVT = VarTemplate->getInstantiatedFromMemberTemplate(); in getTemplateInstantiationPattern() local
2728 if (!NewVT) in getTemplateInstantiationPattern()
2730 VarTemplate = NewVT; in getTemplateInstantiationPattern()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp5991 EVT NewVT = MVT::v4i32; in PerformLOADCombine() local
5992 EVT EltVT = NewVT.getVectorElementType(); in PerformLOADCombine()
5993 unsigned NumElts = NewVT.getVectorNumElements(); in PerformLOADCombine()
5998 SDValue NewLoad = DAG.getMemIntrinsicNode(Opc, DL, RetVTList, Ops, NewVT, in PerformLOADCombine()
6007 {DCI.DAG.getBitcast(VT, DCI.DAG.getBuildVector(NewVT, DL, Elts)), in PerformLOADCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp5576 MVT NewVT = in expandUnalignedRVVLoad()
5578 assert(NewVT.isValid() && in expandUnalignedRVVLoad()
5580 SDValue L = DAG.getLoad(NewVT, DL, Load->getChain(), Load->getBasePtr(), in expandUnalignedRVVLoad()
5607 MVT NewVT = in expandUnalignedRVVStore()
5609 assert(NewVT.isValid() && in expandUnalignedRVVStore()
5611 StoredVal = DAG.getBitcast(NewVT, StoredVal); in expandUnalignedRVVStore()
14162 EVT NewVT = SrcVT.changeVectorElementType(NewEltVT); in narrowIndex()
14164 SDValue NewExt = DAG.getNode(N0->getOpcode(), DL, NewVT, N0->ops()); in narrowIndex()
14165 SDValue NewShAmtVec = DAG.getConstant(ShAmtV, DL, NewVT); in narrowIndex()
14166 N = DAG.getNode(ISD::SHL, DL, NewVT, NewEx in narrowIndex()
5575 MVT NewVT = expandUnalignedRVVLoad() local
5606 MVT NewVT = expandUnalignedRVVStore() local
14159 EVT NewVT = SrcVT.changeVectorElementType(NewEltVT); narrowIndex() local
17359 MVT NewVT = MVT::getIntegerVT(MemVT.getSizeInBits()); PerformDAGCombine() local
17381 MVT NewVT = MVT::getIntegerVT(MemVT.getSizeInBits()); PerformDAGCombine() local
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineCalls.cpp2820 VectorType *NewVT = cast<VectorType>(II->getType()); in visitCallInst() local
2823 Value *V0 = Builder.CreateIntCast(CV0, NewVT, /*isSigned=*/!Zext); in visitCallInst()
2824 Value *V1 = Builder.CreateIntCast(CV1, NewVT, /*isSigned=*/!Zext); in visitCallInst()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h1799 EVT NewVT) const { in shouldReduceLoadWidth() argument
1802 if (NewVT.isVector() && !Load->hasOneUse()) in shouldReduceLoadWidth()

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