| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineRegisterInfo.cpp | 74 const TargetRegisterClass *NewRC = in constrainRegClass() local
76 if (!NewRC || NewRC == OldRC) in constrainRegClass()
77 return NewRC; in constrainRegClass()
78 if (NewRC->getNumRegs() < MinNumRegs) in constrainRegClass()
80 MRI.setRegClass(Reg, NewRC); in constrainRegClass()
81 return NewRC; in constrainRegClass()
126 const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC, *MF); in recomputeRegClass() local
129 if (NewRC == OldRC) in recomputeRegClass()
137 NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII, TRI); in recomputeRegClass()
138 if (!NewRC || NewRC == OldRC) in recomputeRegClass()
[all …]
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| H A D | CriticalAntiDepBreaker.cpp | 187 const TargetRegisterClass *NewRC = nullptr; in PrescanInstruction() local
190 NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF); in PrescanInstruction()
194 if (!Classes[Reg.id()] && NewRC) in PrescanInstruction()
195 Classes[Reg.id()] = NewRC; in PrescanInstruction()
196 else if (!NewRC || Classes[Reg.id()] != NewRC) in PrescanInstruction()
317 const TargetRegisterClass *NewRC = nullptr; in ScanInstruction() local
319 NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF); in ScanInstruction()
323 if (!Classes[Reg.id()] && NewRC) in ScanInstruction()
324 Classes[Reg.id()] = NewRC; in ScanInstruction()
325 else if (!NewRC || Classes[Reg.id()] != NewRC) in ScanInstruction()
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| H A D | RegisterCoalescer.h | 58 const TargetRegisterClass *NewRC = nullptr; variable
82 bool isPhys() const { return !NewRC; } in isPhys()
110 const TargetRegisterClass *getNewRC() const { return NewRC; } in getNewRC()
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| H A D | RegisterCoalescer.cpp | 461 NewRC = nullptr; in setRegisters()
509 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub, SrcIdx, in setRegisters()
511 if (!NewRC) in setRegisters()
516 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub); in setRegisters()
520 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub); in setRegisters()
523 NewRC = TRI.getCommonSubClass(DstRC, SrcRC); in setRegisters()
527 if (!NewRC) in setRegisters()
538 CrossClass = NewRC != DstRC || NewRC != SrcRC; in setRegisters()
1416 const TargetRegisterClass *NewRC = CP.getNewRC(); in reMaterializeTrivialDef() local
1426 NewRC = CommonRC; in reMaterializeTrivialDef()
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| H A D | PeepholeOptimizer.cpp | 1099 const TargetRegisterClass *NewRC = MRI.getRegClass(SrcRegs[0].Reg); in insertPHI() local
1103 Register NewVR = MRI.createVirtualRegister(NewRC); in insertPHI()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURewriteAGPRCopyMFMA.cpp | 65 const TargetRegisterClass *NewRC,
74 const TargetRegisterClass *NewRC, const MachineInstr *ExceptMI) const { in recomputeRegClassExcept() argument
84 NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, &TII, &TRI); in recomputeRegClassExcept()
85 if (!NewRC || NewRC == OldRC) in recomputeRegClassExcept()
89 return NewRC; in recomputeRegClassExcept()
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| H A D | GCNRewritePartialRegUses.cpp | 405 auto *NewRC = getMinSizeReg(RC, SubRegs); in rewriteReg() local
406 if (!NewRC) { in rewriteReg()
411 Register NewReg = MRI->createVirtualRegister(NewRC); in rewriteReg()
415 << TRI->getRegClassName(NewRC) << '\n'); in rewriteReg()
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| H A D | SIRegisterInfo.h | 350 const TargetRegisterClass *NewRC,
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | LazyCallGraph.cpp | 1661 RefSCC *NewRC = OriginalRC; in addSplitFunction() local
1662 NewC = createSCC(*NewRC, SmallVector<Node *, 1>({&NewN})); in addSplitFunction()
1671 int InsertIndex = EK == Edge::Kind::Call ? NewRC->SCCIndices[OriginalC] in addSplitFunction()
1672 : NewRC->SCCIndices.size(); in addSplitFunction()
1673 NewRC->SCCs.insert(NewRC->SCCs.begin() + InsertIndex, NewC); in addSplitFunction()
1674 for (int I = InsertIndex, Size = NewRC->SCCs.size(); I < Size; ++I) in addSplitFunction()
1675 NewRC->SCCIndices[NewRC->SCCs[I]] = I; in addSplitFunction()
1686 RefSCC *NewRC = createRefSCC(*this); in addSplitFunction() local
1687 NewC = createSCC(*NewRC, SmallVector<Node *, 1>({&NewN})); in addSplitFunction()
1688 NewRC->SCCIndices[NewC] = 0; in addSplitFunction()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRRegisterInfo.cpp | 311 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const { in shouldCoalesce() argument
312 if (this->getRegClass(AVR::PTRDISPREGSRegClassID)->hasSubClassEq(NewRC)) { in shouldCoalesce()
317 NewRC, LIS); in shouldCoalesce()
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| H A D | AVRRegisterInfo.h | 56 unsigned DstSubReg, const TargetRegisterClass *NewRC,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.cpp | 388 const TargetRegisterClass *NewRC, in shouldCoalesce() argument
393 if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) && in shouldCoalesce()
421 if (NewRC->contains(SI)) { in shouldCoalesce()
429 if (PhysClobbered.count() > (NewRC->getNumRegs() - DemandedFreeGR128)) in shouldCoalesce()
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| H A D | SystemZRegisterInfo.h | 176 const TargetRegisterClass *NewRC,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.h | 61 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override;
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| H A D | HexagonVLIWPacketizer.h | 146 bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC);
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| H A D | HexagonRegisterInfo.cpp | 351 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const { in shouldCoalesce() argument
358 if (!HST.useHVXOps() || NewRC->getID() != Hexagon::HvxWRRegClass.getID()) in shouldCoalesce()
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| H A D | HexagonFrameLowering.cpp | 2184 const TargetRegisterClass *NewRC) -> const TargetRegisterClass * { in optimizeSpillSlots() argument
2185 if (HaveRC == nullptr || HaveRC == NewRC) in optimizeSpillSlots()
2186 return NewRC; in optimizeSpillSlots()
2188 if (HaveRC->hasSubClassEq(NewRC)) in optimizeSpillSlots()
2190 if (NewRC->hasSubClassEq(HaveRC)) in optimizeSpillSlots()
2191 return NewRC; in optimizeSpillSlots()
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| H A D | HexagonBitSimplify.cpp | 2632 BitTracker::RegisterCell NewRC(W); in simplifyRCmp0() local
2634 NewRC[I] = BitTracker::BitValue(C & 1); in simplifyRCmp0()
2637 BT.put(BitTracker::RegisterRef(NewR), NewRC); in simplifyRCmp0()
2700 BitTracker::RegisterCell NewRC(W); in simplifyRCmp0() local
2701 NewRC[0] = BitTracker::BitValue::self(); in simplifyRCmp0()
2702 NewRC.fill(1, W, BitTracker::BitValue::Zero); in simplifyRCmp0()
2703 BT.put(BitTracker::RegisterRef(NewR), NewRC); in simplifyRCmp0()
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| H A D | HexagonVLIWPacketizer.cpp | 352 const TargetRegisterClass *NewRC) { in isNewifiable() argument
355 if (NewRC == &Hexagon::PredRegsRegClass) { in isNewifiable()
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| H A D | HexagonConstPropagation.cpp | 2900 const TargetRegisterClass *NewRC; in rewriteHexConstDefs() local
2907 NewRC = &Hexagon::IntRegsRegClass; in rewriteHexConstDefs()
2909 NewRC = &Hexagon::DoubleRegsRegClass; in rewriteHexConstDefs()
2910 Register NewR = MRI->createVirtualRegister(NewRC); in rewriteHexConstDefs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86SuppressAPXForReloc.cpp | 75 const TargetRegisterClass *NewRC = RI->constrainRegClassToNonRex2(RC); in suppressEGPRRegClass() local
76 MRI->setRegClass(Reg, NewRC); in suppressEGPRRegClass()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 159 const TargetRegisterClass *NewRC,
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| H A D | ARMBaseRegisterInfo.cpp | 911 const TargetRegisterClass *NewRC, in shouldCoalesce() argument
921 if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 && in shouldCoalesce()
926 MRI.getTargetRegisterInfo()->getRegClassWeight(NewRC); in shouldCoalesce()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.h | 150 unsigned DstSubReg, const TargetRegisterClass *NewRC,
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 1172 const TargetRegisterClass *NewRC, in shouldCoalesce() argument
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