| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineRegisterInfo.cpp | 75 const TargetRegisterClass *NewRC = in constrainRegClass() local
77 if (!NewRC || NewRC == OldRC) in constrainRegClass()
78 return NewRC; in constrainRegClass()
79 if (NewRC->getNumRegs() < MinNumRegs) in constrainRegClass()
81 MRI.setRegClass(Reg, NewRC); in constrainRegClass()
82 return NewRC; in constrainRegClass()
126 const TargetRegisterClass *NewRC = in recomputeRegClass() local
130 if (NewRC == OldRC) in recomputeRegClass()
138 NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII, in recomputeRegClass()
140 if (!NewRC || NewRC == OldRC) in recomputeRegClass()
[all …]
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| H A D | CriticalAntiDepBreaker.cpp | 186 const TargetRegisterClass *NewRC = nullptr; in PrescanInstruction() local
189 NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF); in PrescanInstruction()
193 if (!Classes[Reg] && NewRC) in PrescanInstruction()
194 Classes[Reg] = NewRC; in PrescanInstruction()
195 else if (!NewRC || Classes[Reg] != NewRC) in PrescanInstruction()
314 const TargetRegisterClass *NewRC = nullptr; in ScanInstruction() local
316 NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF); in ScanInstruction()
320 if (!Classes[Reg] && NewRC) in ScanInstruction()
321 Classes[Reg] = NewRC; in ScanInstruction()
322 else if (!NewRC || Classes[Reg] != NewRC) in ScanInstruction()
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| H A D | RegisterCoalescer.h | 57 const TargetRegisterClass *NewRC = nullptr; variable
81 bool isPhys() const { return !NewRC; } in isPhys()
109 const TargetRegisterClass *getNewRC() const { return NewRC; } in getNewRC()
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| H A D | RegisterCoalescer.cpp | 455 NewRC = nullptr; in setRegisters()
501 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub, in setRegisters()
503 if (!NewRC) in setRegisters()
508 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub); in setRegisters()
512 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub); in setRegisters()
515 NewRC = TRI.getCommonSubClass(DstRC, SrcRC); in setRegisters()
519 if (!NewRC) in setRegisters()
530 CrossClass = NewRC != DstRC || NewRC != SrcRC; in setRegisters()
1382 const TargetRegisterClass *NewRC = CP.getNewRC(); in reMaterializeTrivialDef() local
1392 NewRC = CommonRC; in reMaterializeTrivialDef()
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| H A D | PeepholeOptimizer.cpp | 823 const TargetRegisterClass *NewRC = MRI.getRegClass(SrcRegs[0].Reg); in insertPHI() local
827 Register NewVR = MRI.createVirtualRegister(NewRC); in insertPHI()
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | LazyCallGraph.cpp | 1659 RefSCC *NewRC = OriginalRC; in addSplitFunction() local
1660 NewC = createSCC(*NewRC, SmallVector<Node *, 1>({&NewN})); in addSplitFunction()
1669 int InsertIndex = EK == Edge::Kind::Call ? NewRC->SCCIndices[OriginalC] in addSplitFunction()
1670 : NewRC->SCCIndices.size(); in addSplitFunction()
1671 NewRC->SCCs.insert(NewRC->SCCs.begin() + InsertIndex, NewC); in addSplitFunction()
1672 for (int I = InsertIndex, Size = NewRC->SCCs.size(); I < Size; ++I) in addSplitFunction()
1673 NewRC->SCCIndices[NewRC->SCCs[I]] = I; in addSplitFunction()
1684 RefSCC *NewRC = createRefSCC(*this); in addSplitFunction() local
1685 NewC = createSCC(*NewRC, SmallVector<Node *, 1>({&NewN})); in addSplitFunction()
1686 NewRC->SCCIndices[NewC] = 0; in addSplitFunction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNRewritePartialRegUses.cpp | 451 auto *NewRC = getMinSizeReg(RC, SubRegs); in rewriteReg() local
452 if (!NewRC) { in rewriteReg()
457 Register NewReg = MRI->createVirtualRegister(NewRC); in rewriteReg()
461 << TRI->getRegClassName(NewRC) << '\n'); in rewriteReg()
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| H A D | SIRegisterInfo.h | 320 const TargetRegisterClass *NewRC,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRRegisterInfo.cpp | 316 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const { in shouldCoalesce() argument
317 if (this->getRegClass(AVR::PTRDISPREGSRegClassID)->hasSubClassEq(NewRC)) { in shouldCoalesce()
322 NewRC, LIS); in shouldCoalesce()
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| H A D | AVRRegisterInfo.h | 56 unsigned DstSubReg, const TargetRegisterClass *NewRC,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.cpp | 384 const TargetRegisterClass *NewRC, in shouldCoalesce() argument
389 if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) && in shouldCoalesce()
417 if (NewRC->contains(SI)) { in shouldCoalesce()
425 if (PhysClobbered.count() > (NewRC->getNumRegs() - DemandedFreeGR128)) in shouldCoalesce()
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| H A D | SystemZRegisterInfo.h | 175 const TargetRegisterClass *NewRC,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.h | 61 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override;
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| H A D | HexagonVLIWPacketizer.h | 146 bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC);
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| H A D | HexagonRegisterInfo.cpp | 356 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const { in shouldCoalesce() argument
363 if (!HST.useHVXOps() || NewRC->getID() != Hexagon::HvxWRRegClass.getID()) in shouldCoalesce()
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| H A D | HexagonFrameLowering.cpp | 2197 const TargetRegisterClass *NewRC) -> const TargetRegisterClass * { in optimizeSpillSlots() argument
2198 if (HaveRC == nullptr || HaveRC == NewRC) in optimizeSpillSlots()
2199 return NewRC; in optimizeSpillSlots()
2201 if (HaveRC->hasSubClassEq(NewRC)) in optimizeSpillSlots()
2203 if (NewRC->hasSubClassEq(HaveRC)) in optimizeSpillSlots()
2204 return NewRC; in optimizeSpillSlots()
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| H A D | HexagonBitSimplify.cpp | 2654 BitTracker::RegisterCell NewRC(W); in simplifyRCmp0() local
2656 NewRC[I] = BitTracker::BitValue(C & 1); in simplifyRCmp0()
2659 BT.put(BitTracker::RegisterRef(NewR), NewRC); in simplifyRCmp0()
2722 BitTracker::RegisterCell NewRC(W); in simplifyRCmp0() local
2723 NewRC[0] = BitTracker::BitValue::self(); in simplifyRCmp0()
2724 NewRC.fill(1, W, BitTracker::BitValue::Zero); in simplifyRCmp0()
2725 BT.put(BitTracker::RegisterRef(NewR), NewRC); in simplifyRCmp0()
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| H A D | HexagonVLIWPacketizer.cpp | 361 const TargetRegisterClass *NewRC) { in isNewifiable() argument
364 if (NewRC == &Hexagon::PredRegsRegClass) { in isNewifiable()
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| H A D | HexagonConstPropagation.cpp | 2896 const TargetRegisterClass *NewRC; in rewriteHexConstDefs()
2903 NewRC = &Hexagon::IntRegsRegClass; in rewriteHexConstDefs()
2905 NewRC = &Hexagon::DoubleRegsRegClass; in rewriteHexConstDefs()
2906 Register NewR = MRI->createVirtualRegister(NewRC); in rewriteHexConstDefs()
2897 const TargetRegisterClass *NewRC; rewriteHexConstDefs() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.h | 143 unsigned DstSubReg, const TargetRegisterClass *NewRC,
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| H A D | AArch64RegisterInfo.cpp | 1069 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const { in shouldCoalesce() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.cpp | 882 const TargetRegisterClass *NewRC, in shouldCoalesce() argument
892 if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 && in shouldCoalesce()
897 MRI.getTargetRegisterInfo()->getRegClassWeight(NewRC); in shouldCoalesce()
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| H A D | ARMBaseRegisterInfo.h | 234 const TargetRegisterClass *NewRC,
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 1118 const TargetRegisterClass *NewRC, in shouldCoalesce() argument
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| /freebsd/contrib/llvm-project/clang/lib/Sema/ |
| H A D | SemaTemplate.cpp | 7744 const Expr *NewRC = New->getRequiresClause(); in TemplateParameterListsAreEqual() local
7748 Diag(NewRC ? NewRC->getBeginLoc() : New->getTemplateLoc(), in TemplateParameterListsAreEqual()
7754 if (!NewRC != !OldRC) { in TemplateParameterListsAreEqual()
7760 if (NewRC) { in TemplateParameterListsAreEqual()
7762 NewRC)) { in TemplateParameterListsAreEqual()
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