Home
last modified time | relevance | path

Searched refs:NewOpc (Results 1 – 25 of 79) sorted by relevance

1234

/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenMemAbsolute.cpp113 int NewOpc; in runOnMachineFunction() local
114 bool IsLoad = isValidIndexedLoad(NextOpc, NewOpc); in runOnMachineFunction()
116 if (!IsLoad && !isValidIndexedStore(NextOpc, NewOpc)) in runOnMachineFunction()
186 TII->get(NewOpc), LoadStoreReg) in runOnMachineFunction()
191 TII->get(NewOpc), DstReg); in runOnMachineFunction()
217 bool HexagonGenMemAbsolute::isValidIndexedLoad(int &Opc, int &NewOpc) { in isValidIndexedLoad() argument
222 NewOpc = Hexagon::L4_loadrb_ap; in isValidIndexedLoad()
225 NewOpc = Hexagon::L4_loadrh_ap; in isValidIndexedLoad()
228 NewOpc = Hexagon::L4_loadri_ap; in isValidIndexedLoad()
231 NewOpc = Hexagon::L4_loadrd_ap; in isValidIndexedLoad()
[all …]
H A DHexagonRDFOpt.cpp229 unsigned OpNum, NewOpc; in rewrite() local
232 NewOpc = Hexagon::L2_loadri_io; in rewrite()
236 NewOpc = Hexagon::L2_loadrd_io; in rewrite()
240 NewOpc = Hexagon::V6_vL32b_ai; in rewrite()
244 NewOpc = Hexagon::S2_storeri_io; in rewrite()
248 NewOpc = Hexagon::S2_storerd_io; in rewrite()
252 NewOpc = Hexagon::V6_vS32b_ai; in rewrite()
278 MI.setDesc(HII.get(NewOpc)); in rewrite()
H A DHexagonGenPredicate.cpp387 unsigned NewOpc = getPredForm(Opc); in convertToPredForm() local
389 if (NewOpc == 0) { in convertToPredForm()
392 NewOpc = Hexagon::C2_not; in convertToPredForm()
395 NewOpc = TargetOpcode::COPY; in convertToPredForm()
422 MachineInstrBuilder MIB = BuildMI(B, MI, DL, TII->get(NewOpc), NewPR.R); in convertToPredForm()
H A DHexagonCopyToCombine.cpp864 unsigned NewOpc; in emitCombineRR() local
866 NewOpc = Hexagon::A2_combinew; in emitCombineRR()
869 NewOpc = Hexagon::V6_vcombine; in emitCombineRR()
873 BuildMI(*BB, InsertPt, DL, TII->get(NewOpc), DoubleDestReg) in emitCombineRR()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86EncodingOptimization.cpp25 unsigned NewOpc = 0; in optimizeInstFromVEX3ToVEX2() local
28 NewOpc = X86::TO; \ in optimizeInstFromVEX3ToVEX2()
95 if (NewOpc) in optimizeInstFromVEX3ToVEX2()
96 MI.setOpcode(NewOpc); in optimizeInstFromVEX3ToVEX2()
105 unsigned NewOpc; in optimizeShiftRotateWithImmediateOne() local
108 NewOpc = X86::FROM##1; \ in optimizeShiftRotateWithImmediateOne()
111 NewOpc = X86::FROM##1_EVEX; \ in optimizeShiftRotateWithImmediateOne()
114 NewOpc = X86::FROM##1_ND; \ in optimizeShiftRotateWithImmediateOne()
138 NewOpc = X86::FROM##1; \ in optimizeShiftRotateWithImmediateOne()
141 NewOpc = X86::FROM##1_EVEX; \ in optimizeShiftRotateWithImmediateOne()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CompressEVEX.cpp117 static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc) { in performCustomAdjustments() argument
118 (void)NewOpc; in performCustomAdjustments()
125 assert((NewOpc == X86::VPALIGNRrri || NewOpc == X86::VPALIGNRrmi) && in performCustomAdjustments()
141 assert((NewOpc == X86::VPERM2F128rr || NewOpc == X86::VPERM2I128rr || in performCustomAdjustments()
142 NewOpc == X86::VPERM2F128rm || NewOpc == X86::VPERM2I128rm) && in performCustomAdjustments()
236 if (usesExtendedRegister(MI) || !checkPredicate(I->NewOpc, &ST) || in CompressEVEXImpl()
237 !performCustomAdjustments(MI, I->NewOpc)) in CompressEVEXImpl()
239 return I->NewOpc; in CompressEVEXImpl()
243 unsigned NewOpc = IsRedundantNDD in CompressEVEXImpl() local
250 if (!NewOpc) in CompressEVEXImpl()
[all …]
H A DX86FixupInstTuning.cpp106 auto NewOpcPreferable = [&](unsigned NewOpc, in processInstruction()
111 Res = CmpOptionals(GetInstTput(NewOpc), GetInstTput(Opc)); in processInstruction()
115 Res = CmpOptionals(GetInstLat(NewOpc), GetInstLat(Opc)); in processInstruction()
120 Res = CmpOptionals(GetInstSize(Opc), GetInstSize(NewOpc)); in processInstruction()
133 auto ProcessVPERMILPDri = [&](unsigned NewOpc) -> bool { in processInstruction() argument
134 if (!NewOpcPreferable(NewOpc)) in processInstruction()
139 MI.setDesc(TII->get(NewOpc)); in processInstruction()
148 auto ProcessVPERMILPSri = [&](unsigned NewOpc) -> bool { in processInstruction() argument
149 if (!NewOpcPreferable(NewOpc)) in processInstruction()
154 MI.setDesc(TII->get(NewOpc)); in processInstruction()
[all …]
H A DX86EvexToVex.cpp
H A DX86FixupLEAs.cpp810 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); in processInstrForSlow3OpLEA()
816 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA()
822 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA()
848 unsigned NewOpc = in processInstrForSlow3OpLEA()
850 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA()
854 unsigned NewOpc = getADDriFromLEA(MI.getOpcode(), Offset); in processInstrForSlow3OpLEA()
855 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA()
882 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); in processInstrForSlow3OpLEA()
883 NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA()
905 unsigned NewOpc in processInstrForSlow3OpLEA()
809 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); processInstrForSlow3OpLEA() local
847 unsigned NewOpc = processInstrForSlow3OpLEA() local
853 unsigned NewOpc = getADDriFromLEA(MI.getOpcode(), Offset); processInstrForSlow3OpLEA() local
881 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); processInstrForSlow3OpLEA() local
904 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); processInstrForSlow3OpLEA() local
[all...]
H A DX86InstructionSelector.cpp
H A DX86ISelDAGToDAG.cpp1134 unsigned NewOpc; in PreprocessISelDAG() local
1137 case ISD::FP_ROUND: NewOpc = X86ISD::VFPROUND; break; in PreprocessISelDAG()
1138 case ISD::STRICT_FP_ROUND: NewOpc = X86ISD::STRICT_VFPROUND; break; in PreprocessISelDAG()
1139 case ISD::STRICT_FP_TO_SINT: NewOpc = X86ISD::STRICT_CVTTP2SI; break; in PreprocessISelDAG()
1140 case ISD::FP_TO_SINT: NewOpc = X86ISD::CVTTP2SI; break; in PreprocessISelDAG()
1141 case ISD::STRICT_FP_TO_UINT: NewOpc = X86ISD::STRICT_CVTTP2UI; break; in PreprocessISelDAG()
1142 case ISD::FP_TO_UINT: NewOpc = X86ISD::CVTTP2UI; break; in PreprocessISelDAG()
1147 CurDAG->getNode(NewOpc, SDLoc(N), {N->getValueType(0), MVT::Other}, in PreprocessISelDAG()
1151 CurDAG->getNode(NewOpc, SDLoc(N), N->getValueType(0), in PreprocessISelDAG()
1167 unsigned NewOpc; in PreprocessISelDAG() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVExpandPseudoInsts.cpp205 unsigned NewOpc; in expandCCOp() local
209 case RISCV::PseudoCCADD: NewOpc = RISCV::ADD; break; in expandCCOp()
210 case RISCV::PseudoCCSUB: NewOpc = RISCV::SUB; break; in expandCCOp()
211 case RISCV::PseudoCCSLL: NewOpc = RISCV::SLL; break; in expandCCOp()
212 case RISCV::PseudoCCSRL: NewOpc = RISCV::SRL; break; in expandCCOp()
213 case RISCV::PseudoCCSRA: NewOpc = RISCV::SRA; break; in expandCCOp()
214 case RISCV::PseudoCCAND: NewOpc = RISCV::AND; break; in expandCCOp()
215 case RISCV::PseudoCCOR: NewOpc = RISCV::OR; break; in expandCCOp()
216 case RISCV::PseudoCCXOR: NewOpc = RISCV::XOR; break; in expandCCOp()
217 case RISCV::PseudoCCADDI: NewOpc = RISCV::ADDI; break; in expandCCOp()
[all …]
H A DRISCVVectorPeephole.cpp163 NewOpc = RISCV::PseudoVMV_V_V_##lmul; \ in convertVMergeToVMv()
165 unsigned NewOpc; in convertVMergeToVMv() local
189 MI.setDesc(TII->get(NewOpc)); in convertVMergeToVMv()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp685 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, in genInstrWithNewOpc() argument
707 switch (NewOpc) { in genInstrWithNewOpc()
709 NewOpc = Mips::BEQZC; in genInstrWithNewOpc()
712 NewOpc = Mips::BNEZC; in genInstrWithNewOpc()
715 NewOpc = Mips::BGEZC; in genInstrWithNewOpc()
718 NewOpc = Mips::BLTZC; in genInstrWithNewOpc()
721 NewOpc = Mips::BEQZC64; in genInstrWithNewOpc()
724 NewOpc = Mips::BNEZC64; in genInstrWithNewOpc()
729 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc)); in genInstrWithNewOpc()
735 if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 || in genInstrWithNewOpc()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp1349 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode); in MergeBaseUpdateLSMultiple() local
1350 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc)) in MergeBaseUpdateLSMultiple()
1501 unsigned NewOpc; in MergeBaseUpdateLoadStore() local
1503 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::add); in MergeBaseUpdateLoadStore()
1505 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::sub); in MergeBaseUpdateLoadStore()
1511 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::add); in MergeBaseUpdateLoadStore()
1513 (!isAM5 && !isLegalAddressImm(NewOpc, Offset, TII))) { in MergeBaseUpdateLoadStore()
1514 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::sub); in MergeBaseUpdateLoadStore()
1515 if (isAM5 || !isLegalAddressImm(NewOpc, Offset, TII)) in MergeBaseUpdateLoadStore()
1531 auto MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc)) in MergeBaseUpdateLoadStore()
[all …]
H A DARMConstantIslandPass.cpp1845 unsigned NewOpc = 0; in optimizeThumb2Instructions() local
1852 NewOpc = ARM::tLEApcrel; in optimizeThumb2Instructions()
1859 NewOpc = ARM::tLDRpci; in optimizeThumb2Instructions()
1866 if (!NewOpc) in optimizeThumb2Instructions()
1879 U.MI->setDesc(TII->get(NewOpc)); in optimizeThumb2Instructions()
1896 unsigned NewOpc = 0; in optimizeThumb2Branches() local
1902 NewOpc = ARM::tB; in optimizeThumb2Branches()
1907 NewOpc = ARM::tBcc; in optimizeThumb2Branches()
1912 if (NewOpc) { in optimizeThumb2Branches()
1917 Br.MI->setDesc(TII->get(NewOpc)); in optimizeThumb2Branches()
[all …]
H A DThumb2InstrInfo.cpp610 unsigned NewOpc = isSub ? IsSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12 in rewriteT2FrameIndex() local
612 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
643 unsigned NewOpc = Opcode; in rewriteT2FrameIndex() local
653 NewOpc = immediateOffsetOpcode(Opcode); in rewriteT2FrameIndex()
666 NewOpc = negativeOffsetOpcode(Opcode); in rewriteT2FrameIndex()
671 NewOpc = positiveOffsetOpcode(Opcode); in rewriteT2FrameIndex()
731 if (NewOpc != Opcode) in rewriteT2FrameIndex()
732 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
775 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc))); in rewriteT2FrameIndex()
H A DARMInstructionSelector.cpp910 unsigned NewOpc = selectSimpleExtOpc(I.getOpcode(), SrcSize); in select() local
911 if (NewOpc == I.getOpcode()) in select()
913 I.setDesc(TII.get(NewOpc)); in select()
1106 const auto NewOpc = selectLoadStoreOpCode(I.getOpcode(), RegBank, ValSize); in select() local
1107 if (NewOpc == G_LOAD || NewOpc == G_STORE) in select()
1110 I.setDesc(TII.get(NewOpc)); in select()
1112 if (NewOpc == ARM::LDRH || NewOpc == ARM::STRH) in select()
H A DARMExpandPseudoInsts.cpp876 unsigned NewOpc = in ExpandMQQPRLoadStore() local
881 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); in ExpandMQQPRLoadStore()
902 if (NewOpc == ARM::VSTMDIA) in ExpandMQQPRLoadStore()
2144 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBITd : ARM::VBITq; in ExpandMI() local
2145 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)) in ExpandMI()
2154 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBIFd : ARM::VBIFq; in ExpandMI() local
2155 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)) in ExpandMI()
2164 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBSLd : ARM::VBSLq; in ExpandMI() local
2166 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)) in ExpandMI()
2184 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)) in ExpandMI()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostSelectOptimize.cpp270 unsigned NewOpc = getNonFlagSettingVariant(II.getOpcode()); in optimizeNZCVDefs() local
274 if (NewOpc) { in optimizeNZCVDefs()
279 II.setDesc(TII->get(NewOpc)); in optimizeNZCVDefs()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp292 unsigned NewOpc = getTransformOpcode(OldOpc); in transformInstruction() local
293 assert(OldOpc != NewOpc && "transform an instruction to itself?!"); in transformInstruction()
362 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), Dst) in transformInstruction()
H A DAArch64CondBrTuning.cpp98 unsigned NewOpc = TII->convertToFlagSettingOpc(MI.getOpcode()); in convertToFlagSetting() local
104 TII->get(NewOpc), NewDestReg); in convertToFlagSetting()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiMemAluCombiner.cpp251 unsigned NewOpc = mergedOpcode(MemInstr->getOpcode(), AluOffset.isImm()); in insertMergedInstruction()
254 assert(NewOpc != 0 && "Unknown merged node opcode"); in insertMergedInstruction()
258 BuildMI(*BB, MemInstr, MemInstr->getDebugLoc(), TII->get(NewOpc)); in insertMergedInstruction()
252 unsigned NewOpc = mergedOpcode(MemInstr->getOpcode(), AluOffset.isImm()); insertMergedInstruction() local
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp590 unsigned NewOpc = getLoadStoreOp(Ty, RB, Opc, MemOp.getAlign()); in selectLoadStoreOp() local
591 if (NewOpc == Opc) in selectLoadStoreOp()
594 I.setDesc(TII.get(NewOpc)); in selectLoadStoreOp()
655 unsigned NewOpc = getLeaOP(Ty, STI); in selectFrameIndexOrGep() local
656 I.setDesc(TII.get(NewOpc)); in selectFrameIndexOrGep()
706 unsigned NewOpc = getLeaOP(Ty, STI); in selectGlobalValue() local
708 I.setDesc(TII.get(NewOpc)); in selectGlobalValue()
738 unsigned NewOpc; in selectConstant() local
741 NewOpc = X86::MOV8ri; in selectConstant()
744 NewOpc = X86::MOV16ri; in selectConstant()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPostLegalizerCombiner.cpp347 unsigned NewOpc = AMDGPU::G_AMDGPU_CVT_F32_UBYTE0 + MatchInfo.ShiftOffset / 8; in applyCvtF32UByteN() local
357 assert(MI.getOpcode() != NewOpc); in applyCvtF32UByteN()
358 B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags()); in applyCvtF32UByteN()

1234