Lines Matching refs:NewOpc
1349 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode); in MergeBaseUpdateLSMultiple() local
1350 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc)) in MergeBaseUpdateLSMultiple()
1501 unsigned NewOpc; in MergeBaseUpdateLoadStore() local
1503 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::add); in MergeBaseUpdateLoadStore()
1505 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::sub); in MergeBaseUpdateLoadStore()
1511 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::add); in MergeBaseUpdateLoadStore()
1513 (!isAM5 && !isLegalAddressImm(NewOpc, Offset, TII))) { in MergeBaseUpdateLoadStore()
1514 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::sub); in MergeBaseUpdateLoadStore()
1515 if (isAM5 || !isLegalAddressImm(NewOpc, Offset, TII)) in MergeBaseUpdateLoadStore()
1531 auto MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc)) in MergeBaseUpdateLoadStore()
1544 if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) { in MergeBaseUpdateLoadStore()
1546 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg()) in MergeBaseUpdateLoadStore()
1558 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg()) in MergeBaseUpdateLoadStore()
1571 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg()) in MergeBaseUpdateLoadStore()
1585 if (isAM2 && NewOpc == ARM::STR_POST_IMM) { in MergeBaseUpdateLoadStore()
1588 auto MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc), Base) in MergeBaseUpdateLoadStore()
1599 auto MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc), Base) in MergeBaseUpdateLoadStore()
1638 unsigned NewOpc; in MergeBaseUpdateLSDouble() local
1640 NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_PRE : ARM::t2STRD_PRE; in MergeBaseUpdateLSDouble()
1645 NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_POST : ARM::t2STRD_POST; in MergeBaseUpdateLSDouble()
1646 if (!isLegalAddressImm(NewOpc, Offset, TII)) in MergeBaseUpdateLSDouble()
1653 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc)); in MergeBaseUpdateLSDouble()
1654 if (NewOpc == ARM::t2LDRD_PRE || NewOpc == ARM::t2LDRD_POST) { in MergeBaseUpdateLSDouble()
1657 assert(NewOpc == ARM::t2STRD_PRE || NewOpc == ARM::t2STRD_POST); in MergeBaseUpdateLSDouble()
1663 TII->get(NewOpc).getNumOperands() == 7 && in MergeBaseUpdateLSDouble()
1735 bool isDef, unsigned NewOpc, unsigned Reg, in InsertLDR_STR() argument
1742 TII->get(NewOpc)) in InsertLDR_STR()
1751 TII->get(NewOpc)) in InsertLDR_STR()
1807 unsigned NewOpc = (isLd) in FixInvalidRegPairOp() local
1811 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc)) in FixInvalidRegPairOp()
1819 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc)) in FixInvalidRegPairOp()
1831 unsigned NewOpc = (isLd) in FixInvalidRegPairOp() local
1845 InsertLDR_STR(MBB, MBBI, OffImm, isLd, NewOpc, EvenReg, EvenDeadKill, in FixInvalidRegPairOp()
1859 InsertLDR_STR(MBB, MBBI, OffImm, isLd, NewOpc, EvenReg, EvenDeadKill, in FixInvalidRegPairOp()
2059 unsigned NewOpc = (isThumb2 ? ARM::t2LDMIA_RET : ARM::LDMIA_RET); in MergeReturnIntoLDM() local
2062 PrevMI.setDesc(TII->get(NewOpc)); in MergeReturnIntoLDM()
2171 unsigned &NewOpc, Register &EvenReg, Register &OddReg,
2256 MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl, unsigned &NewOpc, in CanFormLdStDWord() argument
2267 NewOpc = ARM::LDRD; in CanFormLdStDWord()
2269 NewOpc = ARM::STRD; in CanFormLdStDWord()
2271 NewOpc = ARM::t2LDRDi8; in CanFormLdStDWord()
2275 NewOpc = ARM::t2STRDi8; in CanFormLdStDWord()
2420 unsigned NewOpc = 0; in RescheduleOps() local
2423 if (NumMove == 2 && CanFormLdStDWord(Op0, Op1, dl, NewOpc, in RescheduleOps()
2429 const MCInstrDesc &MCID = TII->get(NewOpc); in RescheduleOps()