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Searched refs:NZCV (Results 1 – 21 of 21) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostSelectOptimize.cpp267 bool NZCVDead = LRU.available(AArch64::NZCV); in optimizeNZCVDefs()
268 if (NZCVDead && II.definesRegister(AArch64::NZCV, /*TRI=*/nullptr)) { in optimizeNZCVDefs()
272 II.findRegisterDefOperandIdx(AArch64::NZCV, /*TRI=*/nullptr); in optimizeNZCVDefs()
H A DAArch64InstructionSelector.cpp4770 unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(InvOutCC); in emitConditionalComparison() local
4779 CCmp.addImm(NZCV).addImm(Predicate); in emitConditionalComparison()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ConditionalCompares.cpp302 if (!I->readsRegister(AArch64::NZCV, /*TRI=*/nullptr)) { in findConvertibleCompare()
353 PhysRegInfo PRI = AnalyzePhysRegInBundle(*I, AArch64::NZCV, TRI); in findConvertibleCompare()
425 if (&I != CmpMI && I.modifiesRegister(AArch64::NZCV, TRI)) { in canSpeculateInstrs()
686 unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(CmpBBTailCC); in convert() local
699 MIB.addImm(NZCV).addImm(HeadCmpBBCC); in convert()
H A DAArch64RegisterBanks.td18 /// Conditional register: NZCV.
H A DAArch64ConditionOptimizer.cpp157 if (SuccBB->isLiveIn(AArch64::NZCV)) in findSuitableCompare()
166 if (I.readsRegister(AArch64::NZCV, /*TRI=*/nullptr)) in findSuitableCompare()
H A DAArch64InstrInfo.cpp648 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, /*TRI=*/nullptr, in canFoldIntoCSel()
677 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, /*TRI=*/nullptr, in canFoldIntoCSel()
1352 Instr.modifiesRegister(AArch64::NZCV, TRI)) || in areCFlagsAccessedBetweenInstrs()
1353 ((AccessToCheck & AK_Read) && Instr.readsRegister(AArch64::NZCV, TRI))) in areCFlagsAccessedBetweenInstrs()
1507 Pred->addRegisterDefined(AArch64::NZCV, TRI); in optimizePTestInstr()
1511 if (Pred->registerDefIsDead(AArch64::NZCV, TRI)) { in optimizePTestInstr()
1515 if (MO.isReg() && MO.isDef() && MO.getReg() == AArch64::NZCV) { in optimizePTestInstr()
1543 CmpInstr.findRegisterDefOperandIdx(AArch64::NZCV, /*TRI=*/nullptr, true); in optimizeCompareInstr()
1633 if (BB->isLiveIn(AArch64::NZCV)) in areCFlagsAliveInSuccessors()
1647 int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV, /*TRI=*/nullptr); in findCondCodeUseOperandIdxForBranchOrSelect()
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H A DAArch64CondBrTuning.cpp94 if (MO.isReg() && MO.isDead() && MO.getReg() == AArch64::NZCV) in convertToFlagSetting()
H A DAArch64InstrFormats.td1833 // The MRS is set as a NZCV setting instruction. Not all MRS instructions
1837 let Defs = [NZCV];
1840 // FIXME: Some of these def NZCV, others don't. Best way to model that?
1865 let Defs = [NZCV] in
2128 [(AArch64brcond bb:$target, imm:$cond, NZCV)]>, Sched<[WriteBr]> {
2131 let Uses = [NZCV];
2449 let Uses = [NZCV];
2450 let Defs = [NZCV];
2478 let Uses = [NZCV];
2493 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;
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H A DAArch64RedundantCopyElimination.cpp268 if (PredI.definesRegister(AArch64::NZCV, /*TRI=*/nullptr)) in knownRegValInBlock()
H A DAArch64InstrInfo.td1041 let Defs = [SP, NZCV], Uses = [SP] in {
1065 } // Defs = [SP, NZCV], Uses = [SP] in
1170 let Defs = [X16,X17,NZCV];
1836 let Defs = [X16,X17,NZCV];
1853 let Defs = [X16,X17,NZCV];
1958 let Predicates = [HasJS, HasFPARMv8], Defs = [NZCV] in
1967 let Predicates = [HasFlagM], Defs = [NZCV], Uses = [NZCV] in {
1978 let Predicates = [HasAltNZCV], Uses = [NZCV], Defs = [NZCV] in {
2024 let Defs = [ X9, X16, X17, NZCV ], Size = 24 in {
2029 let Uses = [ X9 ], Defs = [ X16, X17, LR, NZCV ] in {
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H A DAArch64SpeculationHardening.cpp236 SplitEdgeBB.addLiveIn(AArch64::NZCV); in insertTrackingCode()
H A DAArch64ExpandPseudoInsts.cpp277 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Kill); in expandCMP_SWAP()
734 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Kill); in expandSetTagLoop()
H A DSVEInstrFormats.td374 let Defs = !if(!eq (opc{0}, 1), [NZCV], []);
781 let Defs = [NZCV];
790 let hasNoSchedulingInfo = 1, isCompare = 1, Defs = [NZCV] in {
816 let Defs = [NZCV];
1867 let Defs = !if(!eq (opc{2}, 1), [NZCV], []);
5142 let Defs = [NZCV];
5232 let Defs = [NZCV];
5306 let Defs = [NZCV];
5350 let Defs = [NZCV];
5372 let Defs = [NZCV];
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H A DAArch64FrameLowering.cpp1114 MBB.isLiveIn(AArch64::NZCV)) in canUseAsPrologue()
2075 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Define | RegState::Dead) in emitPrologue()
2100 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Define | RegState::Dead) in emitPrologue()
4529 if (LiveRegs.contains(AArch64::NZCV)) in tryMergeAdjacentSTG()
H A DAArch64SchedTSV110.td56 // TODO: Use SchedVariant to select BRU for ALU ops that sets NZCV flags
H A DAArch64RegisterInfo.td139 def NZCV : AArch64Reg<0, "nzcv">;
268 def CCR : RegisterClass<"AArch64", [i32], 32, (add NZCV)> {
H A DAArch64Features.td246 "Enable alternative NZCV format for floating point comparisons">;
H A DAArch64ISelLowering.cpp2908 TrueBB->addLiveIn(AArch64::NZCV); in EmitF128CSEL()
2909 EndBB->addLiveIn(AArch64::NZCV); in EmitF128CSEL()
3598 unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(InvOutCC); in emitConditionalComparison() local
3599 SDValue NZCVOp = DAG.getConstant(NZCV, DL, MVT::i32); in emitConditionalComparison()
11553 static SDValue getSETCC(AArch64CC::CondCode CC, SDValue NZCV, const SDLoc &DL, in getSETCC() argument
11558 DAG.getConstant(getInvertedCondCode(CC), DL, MVT::i32), NZCV); in getSETCC()
11575 Glue = DAG.getCopyFromReg(Chain, DL, AArch64::NZCV, MVT::i32, Glue); in LowerAsmOutputForConstraint()
11578 Glue = DAG.getCopyFromReg(Chain, DL, AArch64::NZCV, MVT::i32); in LowerAsmOutputForConstraint()
11729 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass); in getRegForInlineAsmConstraint()
18795 unsigned NZCV; in performANDORCSELCombine() local
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H A DAArch64SchedOryon.td1387 // floating comparison write to NZCV
H A DAArch64SystemOperands.td982 def : RWSysReg<"NZCV", 0b11, 0b011, 0b0100, 0b0010, 0b000>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp140 {codeview::RegisterId::ARM64_NZCV, AArch64::NZCV}, in initLLVMToCVRegMapping()