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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp422 SDValue visitADDLikeCommutative(SDValue N0, SDValue N1,
430 SDValue visitUADDOLike(SDValue N0, SDValue N1, SDNode *N);
436 SDValue visitUADDO_CARRYLike(SDValue N0, SDValue N1, SDValue CarryIn,
438 SDValue visitSADDO_CARRYLike(SDValue N0, SDValue N1, SDValue CarryIn,
447 SDValue visitSDIVLike(SDValue N0, SDValue N1, SDNode *N);
449 SDValue visitUDIVLike(SDValue N0, SDValue N1, SDNode *N);
460 SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *N);
462 SDValue visitORLike(SDValue N0, SDValue N1, const SDLoc &DL);
578 SDValue N1);
580 SDValue N1, SDNodeFlags Flags);
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H A DMatchContext.h120 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, in getNode() argument
125 return DAG.getNode(VPOpcode, DL, VT, {N1, N2, RootMaskOp, RootVectorLenOp}); in getNode()
128 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, in getNode() argument
134 {N1, N2, N3, RootMaskOp, RootVectorLenOp}); in getNode()
146 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, in getNode() argument
151 return DAG.getNode(VPOpcode, DL, VT, {N1, N2, RootMaskOp, RootVectorLenOp}, in getNode()
155 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, in getNode() argument
161 {N1, N2, N3, RootMaskOp, RootVectorLenOp}, Flags); in getNode()
H A DSelectionDAG.cpp2137 static void commuteShuffle(SDValue &N1, SDValue &N2, MutableArrayRef<int> M) { in commuteShuffle() argument
2138 std::swap(N1, N2); in commuteShuffle()
2142 SDValue SelectionDAG::getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, in getVectorShuffle() argument
2146 assert(VT == N1.getValueType() && VT == N2.getValueType() && in getVectorShuffle()
2150 if (N1.isUndef() && N2.isUndef()) in getVectorShuffle()
2164 if (N1 == N2) { in getVectorShuffle()
2171 if (N1.isUndef()) in getVectorShuffle()
2172 commuteShuffle(N1, N2, MaskVec); in getVectorShuffle()
2198 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1)) in getVectorShuffle()
2223 N1 = getUNDEF(VT); in getVectorShuffle()
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H A DTargetLowering.cpp3994 SDValue N1, MutableArrayRef<int> Mask, in buildLegalVectorShuffle() argument
3998 std::swap(N0, N1); in buildLegalVectorShuffle()
4006 return DAG.getVectorShuffle(VT, DL, N0, N1, Mask); in buildLegalVectorShuffle()
4152 SDValue TargetLowering::foldSetCCWithAnd(EVT VT, SDValue N0, SDValue N1, in foldSetCCWithAnd() argument
4155 if (N1.getOpcode() == ISD::AND && N0.getOpcode() != ISD::AND) in foldSetCCWithAnd()
4156 std::swap(N0, N1); in foldSetCCWithAnd()
4166 if (Cond == ISD::SETNE && isNullConstant(N1) && in foldSetCCWithAnd()
4183 if (AndC && isNullConstant(N1) && AndC->getAPIntValue().isPowerOf2() && in foldSetCCWithAnd()
4199 if (N0.getOperand(0) == N1) { in foldSetCCWithAnd()
4202 } else if (N0.getOperand(1) == N1) { in foldSetCCWithAnd()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelDAGToDAG.cpp149 SDValue N1 = Node->getOperand(1); in Select() local
150 auto *C = dyn_cast<ConstantSDNode>(N1); in Select()
154 SDNode *SSL = CurDAG->getMachineNode(Xtensa::SSL, DL, MVT::Glue, N1); in Select()
164 SDValue N1 = Node->getOperand(1); in Select() local
165 auto *C = dyn_cast<ConstantSDNode>(N1); in Select()
180 SDNode *SSR = CurDAG->getMachineNode(Xtensa::SSR, DL, MVT::Glue, N1); in Select()
188 SDValue N1 = Node->getOperand(1); in Select() local
189 auto *C = dyn_cast<ConstantSDNode>(N1); in Select()
193 SDNode *SSR = CurDAG->getMachineNode(Xtensa::SSR, DL, MVT::Glue, N1); in Select()
203 SDValue N1 = Node->getOperand(1); in Select() local
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/freebsd/contrib/llvm-project/libc/src/__support/StringUtil/
H A Dmessage_mapper.h91 template <size_t N1, size_t N2>
92 constexpr MsgTable<N1 + N2> operator+(const MsgTable<N1> &t1,
94 MsgTable<N1 + N2> res{};
95 for (size_t i = 0; i < N1; ++i)
98 res[N1 + i] = t2[i];
/freebsd/crypto/openssl/crypto/bn/asm/
H A Darmv4-mont.pl302 my ($N0,$N1,$N2,$N3)=map("d$_",(4..7));
360 vmlal.u32 @ACC[2],$Ni,${N1}[0]
361 vmlal.u32 @ACC[3],$Ni,${N1}[1]
408 vmlal.u32 @ACC[2],$Ni,${N1}[0]
409 vmlal.u32 @ACC[3],$Ni,${N1}[1]
503 vmlal.u32 @ACC[2],$Ni,${N1}[0]
505 vmlal.u32 @ACC[3],$Ni,${N1}[1]
539 vmlal.u32 @ACC[2],$Ni,${N1}[0]
541 vmlal.u32 @ACC[3],$Ni,${N1}[1]
579 vmlal.u32 @ACC[2],$Ni,${N1}[0]
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H A Dppc64-mont.pl176 $N0="f20"; $N1="f21"; $N2="f22"; $N3="f23";
399 lfd $N1,`$FRAME+104`($sp)
407 fcfid $N1,$N1
424 stfd $N1,48($nap_d)
439 fmadd $T1a,$N1,$na,$T1a
440 fmadd $T1b,$N1,$nb,$T1b
450 fmadd $T2a,$N1,$nc,$T2a
451 fmadd $T2b,$N1,$nd,$T2b
537 lfd $N1,`$FRAME+104`($sp)
545 fcfid $N1,$N1
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H A Darmv8-mont.pl299 my ($A0,$A1,$N0,$N1)=map("v$_",(0..3));
364 ld1 {$N0.4s,$N1.4s},[$nptr],#32
390 umlal @ACC[4].2d,$Ni.2s,$N1.s[0]
393 umlal @ACC[5].2d,$Ni.2s,$N1.s[1]
395 umlal @ACC[6].2d,$Ni.2s,$N1.s[2]
396 umlal @ACC[7].2d,$Ni.2s,$N1.s[3]
430 umlal @ACC[4].2d,$Ni.2s,$N1.s[0]
432 umlal @ACC[5].2d,$Ni.2s,$N1.s[1]
436 umlal @ACC[6].2d,$Ni.2s,$N1.s[2]
437 umlal @ACC[7].2d,$Ni.2s,$N1.s[3]
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/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp111 bool tryIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2, unsigned Opc8,
354 bool MSP430DAGToDAGISel::tryIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2, in tryIndexedBinOp() argument
356 if (N1.getOpcode() == ISD::LOAD && in tryIndexedBinOp()
357 N1.hasOneUse() && in tryIndexedBinOp()
358 IsLegalToFold(N1, Op, Op, OptLevel)) { in tryIndexedBinOp()
359 LoadSDNode *LD = cast<LoadSDNode>(N1); in tryIndexedBinOp()
365 MachineMemOperand *MemRef = cast<MemSDNode>(N1)->getMemOperand(); in tryIndexedBinOp()
371 ReplaceUses(SDValue(N1.getNode(), 2), SDValue(ResNode, 2)); in tryIndexedBinOp()
373 ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1)); in tryIndexedBinOp()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DSDNodeInfoEmitter.cpp54 static bool haveCompatibleDescriptions(const SDNodeInfo &N1, in haveCompatibleDescriptions() argument
57 if (N1.getNumResults() != N2.getNumResults() || in haveCompatibleDescriptions()
58 N1.getNumOperands() != N2.getNumOperands()) in haveCompatibleDescriptions()
62 if (N1.isStrictFP() != N2.isStrictFP() || N1.getTSFlags() != N2.getTSFlags()) in haveCompatibleDescriptions()
72 return (N1.getProperties() & PropMask) == (N2.getProperties() & PropMask); in haveCompatibleDescriptions()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h865 LLVM_ABI SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1,
1216 LLVM_ABI SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
1218 LLVM_ABI SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
1225 LLVM_ABI SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
1227 LLVM_ABI SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
1229 LLVM_ABI SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
1231 LLVM_ABI SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
1234 LLVM_ABI SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
1236 LLVM_ABI SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
1246 SDValue N1, SDValue N2);
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/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Drenesas,rzn1-spi.txt1 Renesas RZ/N1 SPI Controller
8 - compatible : The device specific string followed by the generic RZ/N1 string.
/freebsd/sys/contrib/libsodium/test/default/
H A Dpwhash_scrypt_ll.c7 static const uint64_t N1 = 16U; variable
54 tv(passwd1, salt1, N1, r1, p1); in main()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonCommonGEP.cpp81 bool operator()(const GepNode *N1, const GepNode *N2) const { in operator ()()
82 auto F1 = Map.find(N1), F2 = Map.find(N2); in operator ()()
472 static NodePair node_pair(GepNode *N1, GepNode *N2) { in node_pair() argument
473 uintptr_t P1 = reinterpret_cast<uintptr_t>(N1); in node_pair()
476 return std::make_pair(N1, N2); in node_pair()
477 return std::make_pair(N2, N1); in node_pair()
488 static bool node_eq(GepNode *N1, GepNode *N2, NodePairSet &Eq, in node_eq() argument
492 if (node_hash(N1) != node_hash(N2)) in node_eq()
495 NodePair NP = node_pair(N1, N2); in node_eq()
503 bool Root1 = N1->Flags & GepNode::Root; in node_eq()
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/freebsd/contrib/llvm-project/clang/include/clang/Tooling/ASTDiff/
H A DASTDiff.h105 bool isMatchingAllowed(const Node &N1, const Node &N2) const { in isMatchingAllowed()
106 return N1.getType().isSame(N2.getType()); in isMatchingAllowed()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp4004 SDValue N1 = Node->getOperand(1); in matchBitExtract() local
4007 if (N1 != N01) in matchBitExtract()
4009 canonicalizeShiftAmt(N1, Bitwidth); in matchBitExtract()
4014 if (!checkOneUse(N0, AllowExtraUses) || !checkTwoUse(N1, AllowExtraUses)) in matchBitExtract()
4162 SDValue N1 = Node->getOperand(1); in matchBEXTRFromAndImm() local
4188 auto *MaskCst = dyn_cast<ConstantSDNode>(N1); in matchBEXTRFromAndImm()
4287 SDValue N1 = Node->getOperand(1); in emitPCMPISTR() local
4294 if (MayFoldLoad && tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in emitPCMPISTR()
4296 N1.getOperand(0) }; in emitPCMPISTR()
4300 ReplaceUses(N1.getValue(1), SDValue(CNode, 2)); in emitPCMPISTR()
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H A DX86ISelLowering.cpp6137 SDValue N1 = N.getOperand(1); in getFauxShuffleMask() local
6140 if (!getTargetConstantBitsFromNode(IsAndN ? N0 : N1, 8, UndefElts, EltBits, in getFauxShuffleMask()
6153 Ops.push_back(IsAndN ? N1 : N0); in getFauxShuffleMask()
6160 SDValue N1 = peekThroughBitcasts(N.getOperand(1)); in getFauxShuffleMask() local
6161 if (!N0.getValueType().isVector() || !N1.getValueType().isVector()) in getFauxShuffleMask()
6167 APInt Demand1 = APInt::getAllOnes(N1.getValueType().getVectorNumElements()); in getFauxShuffleMask()
6170 !getTargetShuffleInputs(N1, Demand1, SrcInputs1, SrcMask1, DAG, in getFauxShuffleMask()
6403 SDValue N1 = N.getOperand(1); in getFauxShuffleMask() local
6405 N1.getValueType().getVectorNumElements() == (NumElts / 2) && in getFauxShuffleMask()
6417 (!(N1.isUndef() || EltsRHS.isZero()) && in getFauxShuffleMask()
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/freebsd/sys/arm64/conf/
H A Dstd.arm6 device pci_n1sdp # ARM Neoverse N1 SDP PCI
/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-gxl-s905d-phicomm-n1.dts12 model = "Phicomm N1";
/freebsd/contrib/llvm-project/llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/
H A DScheduler.h33 bool operator()(const DGNode *N1, const DGNode *N2) { in operator()
37 auto *I1 = N1->getInstruction(); in operator()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp7759 SDValue N1 = DAG.getNode(ARMISD::VCVTN, dl, VT, DAG.getUNDEF(VT), Op0, in LowerBuildVectorOfFPTrunc() local
7761 return DAG.getNode(ARMISD::VCVTN, dl, VT, N1, Op1, in LowerBuildVectorOfFPTrunc()
9660 SDNode *N1 = N->getOperand(1).getNode(); in isAddSubSExt() local
9661 return N0->hasOneUse() && N1->hasOneUse() && in isAddSubSExt()
9662 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); in isAddSubSExt()
9671 SDNode *N1 = N->getOperand(1).getNode(); in isAddSubZExt() local
9672 return N0->hasOneUse() && N1->hasOneUse() && in isAddSubZExt()
9673 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); in isAddSubZExt()
9685 SDNode *N1 = Op.getOperand(1).getNode(); in LowerMUL() local
9689 bool isN1SExt = isSignExtended(N1, DAG); in LowerMUL()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp3983 SDValue N1 = N->getOperand(1); in performAssertSZExtCombine() local
3984 EVT ExtVT = cast<VTSDNode>(N1)->getVT(); in performAssertSZExtCombine()
3990 SDValue NewInReg = DAG.getNode(N->getOpcode(), SL, SrcVT, Src, N1); in performAssertSZExtCombine()
4463 SDValue N0, SDValue N1, unsigned Size, bool Signed) { in getMul24() argument
4466 return DAG.getNode(MulOpc, SL, MVT::i32, N0, N1); in getMul24()
4472 SDValue MulLo = DAG.getNode(MulLoOpc, SL, MVT::i32, N0, N1); in getMul24()
4473 SDValue MulHi = DAG.getNode(MulHiOpc, SL, MVT::i32, N0, N1); in getMul24()
4507 SDValue N1 = N->getOperand(1); in performMulCombine() local
4529 SDValue MulVal = DAG.getNode(N->getOpcode(), DL, VT, N1, MulOper); in performMulCombine()
4530 return DAG.getNode(ISD::ADD, DL, VT, MulVal, N1); in performMulCombine()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp1310 SDValue N1 = N->getOperand(1); in isConditionalZeroOrAllOnes() local
1312 if (isZeroOrAllOnes(N1, AllOnes)) { in isConditionalZeroOrAllOnes()
1319 OtherOp = N1; in isConditionalZeroOrAllOnes()
1400 SDValue N1 = N->getOperand(1); in combineSelectAndUseCommutative() local
1402 if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes)) in combineSelectAndUseCommutative()
1404 if (N1.getNode()->hasOneUse()) in combineSelectAndUseCommutative()
1405 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes)) in combineSelectAndUseCommutative()
1414 SDValue N1 = N->getOperand(1); in PerformSUBCombine() local
1417 if (N1.getNode()->hasOneUse()) in PerformSUBCombine()
1418 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, /*AllOnes=*/false)) in PerformSUBCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp549 SDValue N1 = Op.getOperand(1); in isADDADDMUL() local
554 OtherOp = N1; in isADDADDMUL()
555 } else if (N1.getOpcode() == ISD::ADD) { in isADDADDMUL()
556 AddOp = N1; in isADDADDMUL()
1509 SDValue N1 = N->getOperand(1); in PerformDAGCombine() local
1512 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); in PerformDAGCombine()
1517 return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N1, N0, N2); in PerformDAGCombine()
1545 SDValue N1 = N->getOperand(1); in PerformDAGCombine() local
1548 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); in PerformDAGCombine()
1582 SDValue N1 = N->getOperand(1); in PerformDAGCombine() local
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