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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp424 SDValue visitADDLikeCommutative(SDValue N0, SDValue N1, SDNode *LocReference);
430 SDValue visitUADDOLike(SDValue N0, SDValue N1, SDNode *N);
436 SDValue visitUADDO_CARRYLike(SDValue N0, SDValue N1, SDValue CarryIn,
438 SDValue visitSADDO_CARRYLike(SDValue N0, SDValue N1, SDValue CarryIn,
447 SDValue visitSDIVLike(SDValue N0, SDValue N1, SDNode *N);
449 SDValue visitUDIVLike(SDValue N0, SDValue N1, SDNode *N);
460 SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *N);
462 SDValue visitORLike(SDValue N0, SDValue N1, const SDLoc &DL);
574 SDValue N1);
576 SDValue N1, SDNodeFlags Flags);
[all …]
H A DMatchContext.h119 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, in getNode() argument
124 return DAG.getNode(VPOpcode, DL, VT, {N1, N2, RootMaskOp, RootVectorLenOp}); in getNode()
127 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, in getNode() argument
133 {N1, N2, N3, RootMaskOp, RootVectorLenOp}); in getNode()
145 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, in getNode() argument
150 return DAG.getNode(VPOpcode, DL, VT, {N1, N2, RootMaskOp, RootVectorLenOp}, in getNode()
154 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, in getNode() argument
160 {N1, N2, N3, RootMaskOp, RootVectorLenOp}, Flags); in getNode()
H A DSelectionDAG.cpp2080 static void commuteShuffle(SDValue &N1, SDValue &N2, MutableArrayRef<int> M) { in commuteShuffle() argument
2081 std::swap(N1, N2); in commuteShuffle()
2085 SDValue SelectionDAG::getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, in getVectorShuffle() argument
2089 assert(VT == N1.getValueType() && VT == N2.getValueType() && in getVectorShuffle()
2093 if (N1.isUndef() && N2.isUndef()) in getVectorShuffle()
2107 if (N1 == N2) { in getVectorShuffle()
2114 if (N1.isUndef()) in getVectorShuffle()
2115 commuteShuffle(N1, N2, MaskVec); in getVectorShuffle()
2141 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1)) in getVectorShuffle()
2166 N1 = getUNDEF(VT); in getVectorShuffle()
[all …]
H A DTargetLowering.cpp3819 SDValue N1, MutableArrayRef<int> Mask, in buildLegalVectorShuffle() argument
3823 std::swap(N0, N1); in buildLegalVectorShuffle()
3831 return DAG.getVectorShuffle(VT, DL, N0, N1, Mask); in buildLegalVectorShuffle()
3976 SDValue TargetLowering::foldSetCCWithAnd(EVT VT, SDValue N0, SDValue N1, in foldSetCCWithAnd() argument
3979 if (N1.getOpcode() == ISD::AND && N0.getOpcode() != ISD::AND) in foldSetCCWithAnd()
3980 std::swap(N0, N1); in foldSetCCWithAnd()
3990 if (Cond == ISD::SETNE && isNullConstant(N1) && in foldSetCCWithAnd()
4007 if (AndC && isNullConstant(N1) && AndC->getAPIntValue().isPowerOf2() && in foldSetCCWithAnd()
4023 if (N0.getOperand(0) == N1) { in foldSetCCWithAnd()
4026 } else if (N0.getOperand(1) == N1) { in foldSetCCWithAnd()
[all …]
/freebsd/crypto/openssl/crypto/bn/asm/
H A Darmv4-mont.pl302 my ($N0,$N1,$N2,$N3)=map("d$_",(4..7));
360 vmlal.u32 @ACC[2],$Ni,${N1}[0]
361 vmlal.u32 @ACC[3],$Ni,${N1}[1]
408 vmlal.u32 @ACC[2],$Ni,${N1}[0]
409 vmlal.u32 @ACC[3],$Ni,${N1}[1]
503 vmlal.u32 @ACC[2],$Ni,${N1}[0]
505 vmlal.u32 @ACC[3],$Ni,${N1}[1]
539 vmlal.u32 @ACC[2],$Ni,${N1}[0]
541 vmlal.u32 @ACC[3],$Ni,${N1}[1]
579 vmlal.u32 @ACC[2],$Ni,${N1}[0]
[all …]
H A Dppc64-mont.pl176 $N0="f20"; $N1="f21"; $N2="f22"; $N3="f23";
399 lfd $N1,`$FRAME+104`($sp)
407 fcfid $N1,$N1
424 stfd $N1,48($nap_d)
439 fmadd $T1a,$N1,$na,$T1a
440 fmadd $T1b,$N1,$nb,$T1b
450 fmadd $T2a,$N1,$nc,$T2a
451 fmadd $T2b,$N1,$nd,$T2b
537 lfd $N1,`$FRAME+104`($sp)
545 fcfid $N1,$N1
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H A Darmv8-mont.pl297 my ($A0,$A1,$N0,$N1)=map("v$_",(0..3));
362 ld1 {$N0.4s,$N1.4s},[$nptr],#32
388 umlal @ACC[4].2d,$Ni.2s,$N1.s[0]
391 umlal @ACC[5].2d,$Ni.2s,$N1.s[1]
393 umlal @ACC[6].2d,$Ni.2s,$N1.s[2]
394 umlal @ACC[7].2d,$Ni.2s,$N1.s[3]
428 umlal @ACC[4].2d,$Ni.2s,$N1.s[0]
430 umlal @ACC[5].2d,$Ni.2s,$N1.s[1]
434 umlal @ACC[6].2d,$Ni.2s,$N1.s[2]
435 umlal @ACC[7].2d,$Ni.2s,$N1.s[3]
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp115 bool tryIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2, unsigned Opc8,
358 bool MSP430DAGToDAGISel::tryIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2, in tryIndexedBinOp() argument
360 if (N1.getOpcode() == ISD::LOAD && in tryIndexedBinOp()
361 N1.hasOneUse() && in tryIndexedBinOp()
362 IsLegalToFold(N1, Op, Op, OptLevel)) { in tryIndexedBinOp()
363 LoadSDNode *LD = cast<LoadSDNode>(N1); in tryIndexedBinOp()
369 MachineMemOperand *MemRef = cast<MemSDNode>(N1)->getMemOperand(); in tryIndexedBinOp()
375 ReplaceUses(SDValue(N1.getNode(), 2), SDValue(ResNode, 2)); in tryIndexedBinOp()
377 ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1)); in tryIndexedBinOp()
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Drenesas,rzn1-spi.txt1 Renesas RZ/N1 SPI Controller
8 - compatible : The device specific string followed by the generic RZ/N1 string.
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h833 SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue N2,
1149 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
1151 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
1158 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
1160 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
1162 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
1164 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
1171 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1,
1173 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1,
1175 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1,
[all …]
/freebsd/sys/contrib/libsodium/test/default/
H A Dpwhash_scrypt_ll.c7 static const uint64_t N1 = 16U; variable
54 tv(passwd1, salt1, N1, r1, p1); in main()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonCommonGEP.cpp86 bool operator()(const GepNode *N1, const GepNode *N2) const { in operator ()()
87 auto F1 = Map.find(N1), F2 = Map.find(N2); in operator ()()
479 static NodePair node_pair(GepNode *N1, GepNode *N2) { in node_pair() argument
480 uintptr_t P1 = reinterpret_cast<uintptr_t>(N1); in node_pair()
483 return std::make_pair(N1, N2); in node_pair()
484 return std::make_pair(N2, N1); in node_pair()
495 static bool node_eq(GepNode *N1, GepNode *N2, NodePairSet &Eq, in node_eq() argument
499 if (node_hash(N1) != node_hash(N2)) in node_eq()
502 NodePair NP = node_pair(N1, N2); in node_eq()
510 bool Root1 = N1->Flags & GepNode::Root; in node_eq()
[all …]
/freebsd/contrib/llvm-project/clang/include/clang/Tooling/ASTDiff/
H A DASTDiff.h105 bool isMatchingAllowed(const Node &N1, const Node &N2) const { in isMatchingAllowed()
106 return N1.getType().isSame(N2.getType()); in isMatchingAllowed()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp3938 SDValue N1 = Node->getOperand(1); in matchBitExtract() local
3941 if (N1 != N01) in matchBitExtract()
3943 canonicalizeShiftAmt(N1, Bitwidth); in matchBitExtract()
3948 if (!checkOneUse(N0, AllowExtraUses) || !checkTwoUse(N1, AllowExtraUses)) in matchBitExtract()
4096 SDValue N1 = Node->getOperand(1); in matchBEXTRFromAndImm() local
4122 auto *MaskCst = dyn_cast<ConstantSDNode>(N1); in matchBEXTRFromAndImm()
4221 SDValue N1 = Node->getOperand(1); in emitPCMPISTR() local
4228 if (MayFoldLoad && tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in emitPCMPISTR()
4230 N1.getOperand(0) }; in emitPCMPISTR()
4234 ReplaceUses(N1.getValue(1), SDValue(CNode, 2)); in emitPCMPISTR()
[all …]
H A DX86ISelLowering.cpp5842 SDValue N1 = N.getOperand(1); in getFauxShuffleMask() local
5845 if (!getTargetConstantBitsFromNode(IsAndN ? N0 : N1, 8, UndefElts, EltBits, in getFauxShuffleMask()
5858 Ops.push_back(IsAndN ? N1 : N0); in getFauxShuffleMask()
5865 SDValue N1 = peekThroughBitcasts(N.getOperand(1)); in getFauxShuffleMask() local
5866 if (!N0.getValueType().isVector() || !N1.getValueType().isVector()) in getFauxShuffleMask()
5872 APInt Demand1 = APInt::getAllOnes(N1.getValueType().getVectorNumElements()); in getFauxShuffleMask()
5875 !getTargetShuffleInputs(N1, Demand1, SrcInputs1, SrcMask1, DAG, in getFauxShuffleMask()
5898 Ops.push_back(N1); in getFauxShuffleMask()
6086 SDValue N1 = N.getOperand(1); in getFauxShuffleMask() local
6088 N1.getValueType().getVectorNumElements() == (NumElts / 2) && in getFauxShuffleMask()
[all …]
H A DX86OptimizeLEAs.cpp276 int64_t getAddrDispShift(const MachineInstr &MI1, unsigned N1,
398 unsigned N1, in getAddrDispShift() argument
401 const MachineOperand &Op1 = MI1.getOperand(N1 + X86::AddrDisp); in getAddrDispShift()
/freebsd/sys/arm64/conf/
H A Dstd.arm6 device pci_n1sdp # ARM Neoverse N1 SDP PCI
/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-gxl-s905d-phicomm-n1.dts12 model = "Phicomm N1";
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp7709 SDValue N1 = DAG.getNode(ARMISD::VCVTN, dl, VT, DAG.getUNDEF(VT), Op0, in LowerBuildVectorOfFPTrunc() local
7711 return DAG.getNode(ARMISD::VCVTN, dl, VT, N1, Op1, in LowerBuildVectorOfFPTrunc()
9608 SDNode *N1 = N->getOperand(1).getNode(); in isAddSubSExt() local
9609 return N0->hasOneUse() && N1->hasOneUse() && in isAddSubSExt()
9610 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); in isAddSubSExt()
9619 SDNode *N1 = N->getOperand(1).getNode(); in isAddSubZExt() local
9620 return N0->hasOneUse() && N1->hasOneUse() && in isAddSubZExt()
9621 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); in isAddSubZExt()
9633 SDNode *N1 = Op.getOperand(1).getNode(); in LowerMUL() local
9637 bool isN1SExt = isSignExtended(N1, DAG); in LowerMUL()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp3915 SDValue N1 = N->getOperand(1); in performAssertSZExtCombine() local
3916 EVT ExtVT = cast<VTSDNode>(N1)->getVT(); in performAssertSZExtCombine()
3922 SDValue NewInReg = DAG.getNode(N->getOpcode(), SL, SrcVT, Src, N1); in performAssertSZExtCombine()
4235 SDValue N0, SDValue N1, unsigned Size, bool Signed) { in getMul24() argument
4238 return DAG.getNode(MulOpc, SL, MVT::i32, N0, N1); in getMul24()
4244 SDValue MulLo = DAG.getNode(MulLoOpc, SL, MVT::i32, N0, N1); in getMul24()
4245 SDValue MulHi = DAG.getNode(MulHiOpc, SL, MVT::i32, N0, N1); in getMul24()
4279 SDValue N1 = N->getOperand(1); in performMulCombine() local
4301 SDValue MulVal = DAG.getNode(N->getOpcode(), DL, VT, N1, MulOper); in performMulCombine()
4302 return DAG.getNode(ISD::ADD, DL, VT, MulVal, N1); in performMulCombine()
[all …]
H A DAMDGPUISelDAGToDAG.cpp732 SDValue &N0, SDValue &N1) { in getBaseWithOffsetUsingSplitOR() argument
754 N1 = Lo.getOperand(1); in getBaseWithOffsetUsingSplitOR()
1086 SDValue N1 = Addr.getOperand(1); in SelectDS1Addr1Offset() local
1087 ConstantSDNode *C1 = cast<ConstantSDNode>(N1); in SelectDS1Addr1Offset()
1265 SDValue N1 = Addr.getOperand(1); in SelectDSReadWrite2() local
1266 ConstantSDNode *C1 = cast<ConstantSDNode>(N1); in SelectDSReadWrite2()
1651 SDValue N0, N1; in SelectFlatOffsetImpl() local
1652 if (isBaseWithConstantOffset64(Addr, N0, N1) && in SelectFlatOffsetImpl()
1655 int64_t COffsetVal = cast<ConstantSDNode>(N1)->getSExtValue(); in SelectFlatOffsetImpl()
2145 SDValue N0, N1; in SelectSMRDBaseOffset() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp1356 SDValue N1 = N->getOperand(1); in isConditionalZeroOrAllOnes() local
1358 if (isZeroOrAllOnes(N1, AllOnes)) { in isConditionalZeroOrAllOnes()
1365 OtherOp = N1; in isConditionalZeroOrAllOnes()
1446 SDValue N1 = N->getOperand(1); in combineSelectAndUseCommutative() local
1448 if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes)) in combineSelectAndUseCommutative()
1450 if (N1.getNode()->hasOneUse()) in combineSelectAndUseCommutative()
1451 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes)) in combineSelectAndUseCommutative()
1460 SDValue N1 = N->getOperand(1); in PerformSUBCombine() local
1463 if (N1.getNode()->hasOneUse()) in PerformSUBCombine()
1464 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, /*AllOnes=*/false)) in PerformSUBCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp576 SDValue N1 = Op.getOperand(1); in isADDADDMUL() local
581 OtherOp = N1; in isADDADDMUL()
582 } else if (N1.getOpcode() == ISD::ADD) { in isADDADDMUL()
583 AddOp = N1; in isADDADDMUL()
1538 SDValue N1 = N->getOperand(1); in PerformDAGCombine() local
1541 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); in PerformDAGCombine()
1546 return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N1, N0, N2); in PerformDAGCombine()
1574 SDValue N1 = N->getOperand(1); in PerformDAGCombine() local
1577 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); in PerformDAGCombine()
1611 SDValue N1 = N->getOperand(1); in PerformDAGCombine() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp3235 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); in performORCombine() local
3258 N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL && in performORCombine()
3259 (CN1 = dyn_cast<ConstantSDNode>(N1.getOperand(1))) && in performORCombine()
3262 (CN1 = dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(1))) && in performORCombine()
3267 N1.getOperand(0).getOperand(0), in performORCombine()
3280 N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::AND && in performORCombine()
3281 (CN1 = dyn_cast<ConstantSDNode>(N1.getOperand(1))) && in performORCombine()
3283 (CN1 = dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(1))) && in performORCombine()
3289 N1.getOperand(0).getOperand(0), in performORCombine()
3300 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::AND && in performORCombine()
[all …]
/freebsd/contrib/llvm-project/clang/lib/AST/
H A DASTStructuralEquivalence.cpp581 const TemplateName &N1, in IsStructurallyEquivalent() argument
583 TemplateDecl *TemplateDeclN1 = N1.getAsTemplateDecl(); in IsStructurallyEquivalent()
589 if (N1.getKind() != N2.getKind()) in IsStructurallyEquivalent()
593 else if (N1.getKind() != N2.getKind()) in IsStructurallyEquivalent()
597 switch (N1.getKind()) { in IsStructurallyEquivalent()
600 OverloadedTemplateStorage *OS1 = N1.getAsOverloadedTemplate(), in IsStructurallyEquivalent()
611 AssumedTemplateStorage *TN1 = N1.getAsAssumedTemplateName(), in IsStructurallyEquivalent()
612 *TN2 = N1.getAsAssumedTemplateName(); in IsStructurallyEquivalent()
617 DependentTemplateName *DN1 = N1.getAsDependentTemplateName(), in IsStructurallyEquivalent()
632 *P1 = N1.getAsSubstTemplateTemplateParmPack(), in IsStructurallyEquivalent()

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