Lines Matching refs:N1
7709 SDValue N1 = DAG.getNode(ARMISD::VCVTN, dl, VT, DAG.getUNDEF(VT), Op0, in LowerBuildVectorOfFPTrunc() local
7711 return DAG.getNode(ARMISD::VCVTN, dl, VT, N1, Op1, in LowerBuildVectorOfFPTrunc()
9608 SDNode *N1 = N->getOperand(1).getNode(); in isAddSubSExt() local
9609 return N0->hasOneUse() && N1->hasOneUse() && in isAddSubSExt()
9610 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); in isAddSubSExt()
9619 SDNode *N1 = N->getOperand(1).getNode(); in isAddSubZExt() local
9620 return N0->hasOneUse() && N1->hasOneUse() && in isAddSubZExt()
9621 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); in isAddSubZExt()
9633 SDNode *N1 = Op.getOperand(1).getNode(); in LowerMUL() local
9637 bool isN1SExt = isSignExtended(N1, DAG); in LowerMUL()
9642 bool isN1ZExt = isZeroExtended(N1, DAG); in LowerMUL()
9654 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) { in LowerMUL()
9655 std::swap(N0, N1); in LowerMUL()
9674 SDValue Op1 = SkipExtensionForVMULL(N1, DAG); in LowerMUL()
9732 static SDValue LowerSDIV_v4i16(SDValue N0, SDValue N1, const SDLoc &dl, in LowerSDIV_v4i16() argument
9741 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1); in LowerSDIV_v4i16()
9743 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1); in LowerSDIV_v4i16()
9750 N1); in LowerSDIV_v4i16()
9751 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, in LowerSDIV_v4i16()
9753 N1, N2); in LowerSDIV_v4i16()
9754 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); in LowerSDIV_v4i16()
9761 N1 = DAG.getConstant(0x89, dl, MVT::v4i32); in LowerSDIV_v4i16()
9762 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); in LowerSDIV_v4i16()
9779 SDValue N1 = Op.getOperand(1); in LowerSDIV() local
9784 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1); in LowerSDIV()
9788 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerSDIV()
9792 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerSDIV()
9795 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16 in LowerSDIV()
9804 return LowerSDIV_v4i16(N0, N1, dl, DAG); in LowerSDIV()
9816 SDValue N1 = Op.getOperand(1); in LowerUDIV() local
9821 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1); in LowerUDIV()
9825 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerUDIV()
9829 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerUDIV()
9832 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16 in LowerUDIV()
9849 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1); in LowerUDIV()
9851 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1); in LowerUDIV()
9860 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, in LowerUDIV()
9863 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); in LowerUDIV()
9864 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, in LowerUDIV()
9867 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); in LowerUDIV()
9874 N1 = DAG.getConstant(2, dl, MVT::v4i32); in LowerUDIV()
9875 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); in LowerUDIV()
12526 SDValue N1 = N->getOperand(1); in isConditionalZeroOrAllOnes() local
12528 if (isZeroOrAllOnes(N1, AllOnes)) { in isConditionalZeroOrAllOnes()
12535 OtherOp = N1; in isConditionalZeroOrAllOnes()
12620 SDValue N1 = N->getOperand(1); in combineSelectAndUseCommutative() local
12622 if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes)) in combineSelectAndUseCommutative()
12624 if (N1.getNode()->hasOneUse()) in combineSelectAndUseCommutative()
12625 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes)) in combineSelectAndUseCommutative()
12642 static SDValue AddCombineToVPADD(SDNode *N, SDValue N0, SDValue N1, in AddCombineToVPADD() argument
12646 if (!IsVUZPShuffleNode(N0.getNode()) || N0.getNode() != N1.getNode() || in AddCombineToVPADD()
12647 N0 == N1) in AddCombineToVPADD()
12670 static SDValue AddCombineVUZPToVPADDL(SDNode *N, SDValue N0, SDValue N1, in AddCombineVUZPToVPADDL() argument
12675 N1.getOpcode() == ISD::SIGN_EXTEND) && in AddCombineVUZPToVPADDL()
12677 N1.getOpcode() == ISD::ZERO_EXTEND)) in AddCombineVUZPToVPADDL()
12681 SDValue N10 = N1.getOperand(0); in AddCombineVUZPToVPADDL()
12723 AddCombineBUILD_VECTORToVPADDL(SDNode *N, SDValue N0, SDValue N1, in AddCombineBUILD_VECTORToVPADDL() argument
12730 || N1.getOpcode() != ISD::BUILD_VECTOR) in AddCombineBUILD_VECTORToVPADDL()
12756 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in AddCombineBUILD_VECTORToVPADDL()
12759 SDValue ExtVec1 = N1->getOperand(i); in AddCombineBUILD_VECTORToVPADDL()
13367 ConstantSDNode *N1 = isConstOrConstSplat(Shft.getOperand(1)); in PerformVQDMULHCombine() local
13368 if (!N1 || N1->getSExtValue() != ShftAmt) in PerformVQDMULHCombine()
13545 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1, in PerformADDCombineWithOperands() argument
13549 if (SDValue Result = AddCombineToVPADD(N, N0, N1, DCI, Subtarget)) in PerformADDCombineWithOperands()
13553 if (SDValue Result = AddCombineVUZPToVPADDL(N, N0, N1, DCI, Subtarget)) in PerformADDCombineWithOperands()
13555 if (SDValue Result = AddCombineBUILD_VECTORToVPADDL(N, N0, N1, DCI, in PerformADDCombineWithOperands()
13561 if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI)) in PerformADDCombineWithOperands()
13569 SDValue N1 = N->getOperand(1); in TryDistrubutionADDVecReduce() local
13584 auto DistrubuteAddAddVecReduce = [&](SDValue N0, SDValue N1) { in TryDistrubutionADDVecReduce() argument
13588 if (VT == MVT::i32 && N1.getOpcode() == ISD::ADD && !IsVecReduce(N0) && in TryDistrubutionADDVecReduce()
13589 IsVecReduce(N1.getOperand(0)) && IsVecReduce(N1.getOperand(1)) && in TryDistrubutionADDVecReduce()
13590 !isa<ConstantSDNode>(N0) && N1->hasOneUse()) { in TryDistrubutionADDVecReduce()
13591 SDValue Add0 = DAG.getNode(ISD::ADD, dl, VT, N0, N1.getOperand(0)); in TryDistrubutionADDVecReduce()
13592 return DAG.getNode(ISD::ADD, dl, VT, Add0, N1.getOperand(1)); in TryDistrubutionADDVecReduce()
13597 N1.getOpcode() == ISD::ADD && N0->hasOneUse() && N1->hasOneUse()) { in TryDistrubutionADDVecReduce()
13606 if (!IsVecReduce(N1.getOperand(N1RedOp))) in TryDistrubutionADDVecReduce()
13608 if (!IsVecReduce(N1.getOperand(N1RedOp))) in TryDistrubutionADDVecReduce()
13612 N1.getOperand(1 - N1RedOp)); in TryDistrubutionADDVecReduce()
13615 return DAG.getNode(ISD::ADD, dl, VT, Add1, N1.getOperand(N1RedOp)); in TryDistrubutionADDVecReduce()
13619 if (SDValue R = DistrubuteAddAddVecReduce(N0, N1)) in TryDistrubutionADDVecReduce()
13621 if (SDValue R = DistrubuteAddAddVecReduce(N1, N0)) in TryDistrubutionADDVecReduce()
13628 auto DistrubuteVecReduceLoad = [&](SDValue N0, SDValue N1, bool IsForward) { in TryDistrubutionADDVecReduce() argument
13632 auto IsKnownOrderedLoad = [&](SDValue N0, SDValue N1) { in TryDistrubutionADDVecReduce() argument
13637 if (N1.getOpcode() == ISD::MUL) in TryDistrubutionADDVecReduce()
13638 N1 = N1.getOperand(0); in TryDistrubutionADDVecReduce()
13643 LoadSDNode *Load1 = dyn_cast<LoadSDNode>(N1); in TryDistrubutionADDVecReduce()
13684 } else if (IsForward && IsVecReduce(N0) && IsVecReduce(N1) && in TryDistrubutionADDVecReduce()
13685 IsKnownOrderedLoad(N0.getOperand(0), N1.getOperand(0)) < 0) { in TryDistrubutionADDVecReduce()
13690 return DAG.getNode(ISD::ADD, dl, VT, N1, N0); in TryDistrubutionADDVecReduce()
13694 if (!IsVecReduce(N0) || !IsVecReduce(N1)) in TryDistrubutionADDVecReduce()
13697 if (IsKnownOrderedLoad(N1.getOperand(0), N0.getOperand(0)) >= 0) in TryDistrubutionADDVecReduce()
13701 SDValue Add0 = DAG.getNode(ISD::ADD, dl, VT, X, N1); in TryDistrubutionADDVecReduce()
13704 if (SDValue R = DistrubuteVecReduceLoad(N0, N1, true)) in TryDistrubutionADDVecReduce()
13706 if (SDValue R = DistrubuteVecReduceLoad(N1, N0, false)) in TryDistrubutionADDVecReduce()
13721 SDValue N1 = N->getOperand(1); in PerformADDVecReduce() local
13764 if (SDValue M = MakeVecReduce(ARMISD::VADDLVs, ARMISD::VADDLVAs, N0, N1)) in PerformADDVecReduce()
13766 if (SDValue M = MakeVecReduce(ARMISD::VADDLVu, ARMISD::VADDLVAu, N0, N1)) in PerformADDVecReduce()
13768 if (SDValue M = MakeVecReduce(ARMISD::VADDLVs, ARMISD::VADDLVAs, N1, N0)) in PerformADDVecReduce()
13770 if (SDValue M = MakeVecReduce(ARMISD::VADDLVu, ARMISD::VADDLVAu, N1, N0)) in PerformADDVecReduce()
13772 if (SDValue M = MakeVecReduce(ARMISD::VADDLVps, ARMISD::VADDLVAps, N0, N1)) in PerformADDVecReduce()
13774 if (SDValue M = MakeVecReduce(ARMISD::VADDLVpu, ARMISD::VADDLVApu, N0, N1)) in PerformADDVecReduce()
13776 if (SDValue M = MakeVecReduce(ARMISD::VADDLVps, ARMISD::VADDLVAps, N1, N0)) in PerformADDVecReduce()
13778 if (SDValue M = MakeVecReduce(ARMISD::VADDLVpu, ARMISD::VADDLVApu, N1, N0)) in PerformADDVecReduce()
13780 if (SDValue M = MakeVecReduce(ARMISD::VMLALVs, ARMISD::VMLALVAs, N0, N1)) in PerformADDVecReduce()
13782 if (SDValue M = MakeVecReduce(ARMISD::VMLALVu, ARMISD::VMLALVAu, N0, N1)) in PerformADDVecReduce()
13784 if (SDValue M = MakeVecReduce(ARMISD::VMLALVs, ARMISD::VMLALVAs, N1, N0)) in PerformADDVecReduce()
13786 if (SDValue M = MakeVecReduce(ARMISD::VMLALVu, ARMISD::VMLALVAu, N1, N0)) in PerformADDVecReduce()
13788 if (SDValue M = MakeVecReduce(ARMISD::VMLALVps, ARMISD::VMLALVAps, N0, N1)) in PerformADDVecReduce()
13790 if (SDValue M = MakeVecReduce(ARMISD::VMLALVpu, ARMISD::VMLALVApu, N0, N1)) in PerformADDVecReduce()
13792 if (SDValue M = MakeVecReduce(ARMISD::VMLALVps, ARMISD::VMLALVAps, N1, N0)) in PerformADDVecReduce()
13794 if (SDValue M = MakeVecReduce(ARMISD::VMLALVpu, ARMISD::VMLALVApu, N1, N0)) in PerformADDVecReduce()
13818 SDValue N1 = N->getOperand(0); in isDesirableToCommuteWithShift() local
13819 if (N1->getOpcode() != ISD::ADD && N1->getOpcode() != ISD::AND && in isDesirableToCommuteWithShift()
13820 N1->getOpcode() != ISD::OR && N1->getOpcode() != ISD::XOR) in isDesirableToCommuteWithShift()
13822 if (auto *Const = dyn_cast<ConstantSDNode>(N1->getOperand(1))) { in isDesirableToCommuteWithShift()
13825 if (N1->getOpcode() == ISD::ADD && Const->getAPIntValue().slt(0) && in isDesirableToCommuteWithShift()
14026 SDValue N1 = N->getOperand(1); in PerformADDCombine() local
14036 if (SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget)) in PerformADDCombine()
14040 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget); in PerformADDCombine()
14069 SDValue N1 = N->getOperand(1); in PerformSUBCombine() local
14072 if (N1.getNode()->hasOneUse()) in PerformSUBCombine()
14073 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI)) in PerformSUBCombine()
14126 SDValue N1 = N->getOperand(1); in PerformVMULCombine() local
14130 Opcode = N1.getOpcode(); in PerformVMULCombine()
14134 std::swap(N0, N1); in PerformVMULCombine()
14137 if (N0 == N1) in PerformVMULCombine()
14145 DAG.getNode(ISD::MUL, DL, VT, N00, N1), in PerformVMULCombine()
14146 DAG.getNode(ISD::MUL, DL, VT, N01, N1)); in PerformVMULCombine()
14156 SDValue N1 = N->getOperand(1); in PerformMVEVMULLCombine() local
14197 if (SDValue Op1 = IsSignExt(N1)) { in PerformMVEVMULLCombine()
14204 if (SDValue Op1 = IsZeroExt(N1)) { in PerformMVEVMULLCombine()
14531 SDValue N1 = N->getOperand(1); in PerformORCombineToBFI() local
14561 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); in PerformORCombineToBFI()
14579 } else if (N1.getOpcode() == ISD::AND) { in PerformORCombineToBFI()
14581 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); in PerformORCombineToBFI()
14597 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0), in PerformORCombineToBFI()
14616 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res, in PerformORCombineToBFI()
14625 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) && in PerformORCombineToBFI()
14636 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0), in PerformORCombineToBFI()
14686 SDValue N1 = N->getOperand(1); in PerformORCombine_i1() local
14695 if (!(IsFreelyInvertable(N0) || IsFreelyInvertable(N1))) in PerformORCombine_i1()
14699 SDValue NewN1 = DAG.getLogicalNOT(DL, N1, VT); in PerformORCombine_i1()
14750 SDValue N1 = N->getOperand(1); in PerformORCombine() local
14753 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() && in PerformORCombine()
14768 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1)); in PerformORCombine()
14785 N1->getOperand(0)); in PerformORCombine()
14826 SDValue N1 = N->getOperand(1); in PerformXORCombine() local
14828 if (TLI->isConstTrueVal(N1) && in PerformXORCombine()
14912 SDValue N1 = N->getOperand(1); in PerformBFICombine() local
14914 if (N1.getOpcode() == ISD::AND) { in PerformBFICombine()
14917 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); in PerformBFICombine()
14930 N->getOperand(0), N1.getOperand(0), N->getOperand(2)); in PerformBFICombine()