| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsExpandPseudo.cpp | 106 Register Mask2 = I->getOperand(4).getReg(); in expandAtomicCmpSwapSubword() local
159 .addReg(Mask2); in expandAtomicCmpSwapSubword()
431 Register Mask2 = I->getOperand(4).getReg(); in expandAtomicBinOpSubword() local
569 .addReg(OldVal).addReg(Mask2); in expandAtomicBinOpSubword()
|
| H A D | MipsISelLowering.cpp | 1695 Register Mask2 = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword() local
1827 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); in emitAtomicBinaryPartword()
1841 .addReg(Mask2) in emitAtomicBinaryPartword()
1944 Register Mask2 = RegInfo.createVirtualRegister(RC); in emitAtomicCmpSwapPartword() local
2014 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); in emitAtomicCmpSwapPartword()
2033 .addReg(Mask2) in emitAtomicCmpSwapPartword()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMSystemRegister.td | 45 // Mask1 Mask2 Mask3 Enc12, Name
|
| H A D | ARMISelLowering.cpp | 6101 SDValue Mask2 = DAG.getConstant(0x7fffffff, dl, MVT::i32); in LowerFCOPYSIGN() local
6105 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2); in LowerFCOPYSIGN()
6114 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2); in LowerFCOPYSIGN()
14584 unsigned Mask2 = N11C->getZExtValue(); in PerformORCombineToBFI() local
14589 (Mask == ~Mask2)) { in PerformORCombineToBFI()
14596 unsigned amt = llvm::countr_zero(Mask2); in PerformORCombineToBFI()
14606 (~Mask == Mask2)) { in PerformORCombineToBFI()
14610 (Mask2 == 0xffff || Mask2 == 0xffff0000)) in PerformORCombineToBFI()
14617 DAG.getConstant(Mask2, DL, MVT::i32)); in PerformORCombineToBFI()
14927 unsigned Mask2 = N11C->getZExtValue(); in PerformBFICombine() local
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VPlanTransforms.cpp | 238 VPValue *Mask2 = getPredicatedMask(Region2); in mergeReplicateRegionsIntoSuccessors() local
239 if (!Mask1 || Mask1 != Mask2) in mergeReplicateRegionsIntoSuccessors()
242 assert(Mask1 && Mask2 && "both region must have conditions"); in mergeReplicateRegionsIntoSuccessors()
|
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSimplifyDemanded.cpp | 873 APInt Mask2 = LowBits | APInt::getSignMask(BitWidth); in SimplifyDemandedUseBits() local
874 if (SimplifyDemandedBits(I, 0, Mask2, LHSKnown, Depth + 1, Q)) in SimplifyDemandedUseBits()
|
| H A D | InstCombineCompares.cpp | 3647 APInt Mask2 = IsTrailing in foldICmpEqIntrinsicWithConstant() local
3651 ConstantInt::get(Ty, Mask2)); in foldICmpEqIntrinsicWithConstant()
|
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | SROA.cpp | 2588 SmallVector<Constant *, 8> Mask2; in insertVector() local
2589 Mask2.reserve(cast<FixedVectorType>(VecTy)->getNumElements()); in insertVector()
2591 Mask2.push_back(IRB.getInt1(i >= BeginIndex && i < EndIndex)); in insertVector()
2593 V = IRB.CreateSelect(ConstantVector::get(Mask2), V, Old, Name + "blend"); in insertVector()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAGHVX.cpp | 2098 auto same = [](ArrayRef<int> Mask1, ArrayRef<int> Mask2) -> bool { in contracting()
2099 return Mask1 == Mask2; in contracting()
2100 __anon9fc097471602(ArrayRef<int> Mask1, ArrayRef<int> Mask2) contracting() argument
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 9510 APInt Mask2 = APInt::getSplat(Sz, APInt(8, 0x33)); in expandBITREVERSE() local
9525 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(Mask2, dl, VT)); in expandBITREVERSE()
9526 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(Mask2, dl, VT)); in expandBITREVERSE()
9575 APInt Mask2 = APInt::getSplat(Sz, APInt(8, 0x33)); in expandVPBITREVERSE() local
9596 DAG.getConstant(Mask2, dl, VT), Mask, EVL); in expandVPBITREVERSE()
9597 Tmp3 = DAG.getNode(ISD::VP_AND, dl, VT, Tmp, DAG.getConstant(Mask2, dl, VT), in expandVPBITREVERSE()
|
| /freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 17168 Value *Mask2 = ConstantVector::get(Consts); in EmitPPCBuiltinExpr() local
17170 Builder.CreateCall(Vperm, {Zero, AllElts, Mask2}, "shuffle2"), ResTy); in EmitPPCBuiltinExpr()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 13093 SDValue Mask2 = Tbl2->getOperand(3); in tryToConvertShuffleOfTbl2ToTbl4() local
13100 dyn_cast<ConstantSDNode>(Mask2->getOperand(ShuffleMask[I] - 16)); in tryToConvertShuffleOfTbl2ToTbl4()
|