| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUWaitSGPRHazards.cpp | 167 unsigned mergeMasks(unsigned Mask1, unsigned Mask2) { in mergeMasks() argument
171 AMDGPU::DepCtr::decodeFieldSaSdst(Mask2))); in mergeMasks()
174 AMDGPU::DepCtr::decodeFieldVaVcc(Mask2))); in mergeMasks()
177 AMDGPU::DepCtr::decodeFieldVmVsrc(Mask2))); in mergeMasks()
180 AMDGPU::DepCtr::decodeFieldVaSdst(Mask2))); in mergeMasks()
183 AMDGPU::DepCtr::decodeFieldVaVdst(Mask2))); in mergeMasks()
186 AMDGPU::DepCtr::decodeFieldHoldCnt(Mask2))); in mergeMasks()
189 AMDGPU::DepCtr::decodeFieldVaSsrc(Mask2))); in mergeMasks()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsExpandPseudo.cpp | 105 Register Mask2 = I->getOperand(4).getReg(); in expandAtomicCmpSwapSubword() local
158 .addReg(Mask2); in expandAtomicCmpSwapSubword()
430 Register Mask2 = I->getOperand(4).getReg(); in expandAtomicBinOpSubword() local
638 .addReg(Mask2); in expandAtomicBinOpSubword()
653 .addReg(Mask2); in expandAtomicBinOpSubword()
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| H A D | MipsISelLowering.cpp | 1790 Register Mask2 = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword() local
1922 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); in emitAtomicBinaryPartword()
1936 .addReg(Mask2) in emitAtomicBinaryPartword()
2039 Register Mask2 = RegInfo.createVirtualRegister(RC); in emitAtomicCmpSwapPartword() local
2109 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); in emitAtomicCmpSwapPartword()
2128 .addReg(Mask2) in emitAtomicCmpSwapPartword()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMSystemRegister.td | 62 // Mask1 Mask2 Mask3 Enc12, Name
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| H A D | ARMISelLowering.cpp | 6174 SDValue Mask2 = DAG.getConstant(0x7fffffff, dl, MVT::i32); in LowerFCOPYSIGN() local
6178 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2); in LowerFCOPYSIGN()
6187 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2); in LowerFCOPYSIGN()
14661 unsigned Mask2 = N11C->getZExtValue(); in PerformORCombineToBFI() local
14666 (Mask == ~Mask2)) { in PerformORCombineToBFI()
14673 unsigned amt = llvm::countr_zero(Mask2); in PerformORCombineToBFI()
14683 (~Mask == Mask2)) { in PerformORCombineToBFI()
14687 (Mask2 == 0xffff || Mask2 == 0xffff0000)) in PerformORCombineToBFI()
14694 DAG.getConstant(Mask2, DL, MVT::i32)); in PerformORCombineToBFI()
15004 unsigned Mask2 = N11C->getZExtValue(); in PerformBFICombine() local
[all …]
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| /freebsd/contrib/llvm-project/clang/lib/CodeGen/TargetBuiltins/ |
| H A D | PPC.cpp | 411 Value *Mask2 = ConstantVector::get(Consts); in EmitPPCBuiltinExpr() local
413 Builder.CreateCall(Vperm, {Zero, AllElts, Mask2}, "shuffle2"), ResTy); in EmitPPCBuiltinExpr()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSimplifyDemanded.cpp | 891 APInt Mask2 = LowBits | APInt::getSignMask(BitWidth); in SimplifyDemandedUseBits() local
892 if (SimplifyDemandedBits(I, 0, Mask2, LHSKnown, Q, Depth + 1)) in SimplifyDemandedUseBits()
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| H A D | InstCombineCompares.cpp | 3840 APInt Mask2 = IsTrailing in foldICmpEqIntrinsicWithConstant() local
3844 ConstantInt::get(Ty, Mask2)); in foldICmpEqIntrinsicWithConstant()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VPlanTransforms.cpp | 267 VPValue *Mask2 = getPredicatedMask(Region2); in mergeReplicateRegionsIntoSuccessors() local
268 if (!Mask1 || Mask1 != Mask2) in mergeReplicateRegionsIntoSuccessors()
271 assert(Mask1 && Mask2 && "both region must have conditions"); in mergeReplicateRegionsIntoSuccessors()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | SROA.cpp | 2684 SmallVector<Constant *, 8> Mask2; in insertVector() local
2685 Mask2.reserve(cast<FixedVectorType>(VecTy)->getNumElements()); in insertVector()
2687 Mask2.push_back(IRB.getInt1(i >= BeginIndex && i < EndIndex)); in insertVector()
2689 V = IRB.CreateSelect(ConstantVector::get(Mask2), V, Old, Name + "blend"); in insertVector()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAGHVX.cpp | 2089 auto same = [](ArrayRef<int> Mask1, ArrayRef<int> Mask2) -> bool { in contracting() argument
2090 return Mask1 == Mask2; in contracting()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 10005 APInt Mask2 = APInt::getSplat(Sz, APInt(8, 0x33)); in expandBITREVERSE() local
10020 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(Mask2, dl, VT)); in expandBITREVERSE()
10021 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(Mask2, dl, VT)); in expandBITREVERSE()
10070 APInt Mask2 = APInt::getSplat(Sz, APInt(8, 0x33)); in expandVPBITREVERSE() local
10091 DAG.getConstant(Mask2, dl, VT), Mask, EVL); in expandVPBITREVERSE()
10092 Tmp3 = DAG.getNode(ISD::VP_AND, dl, VT, Tmp, DAG.getConstant(Mask2, dl, VT), in expandVPBITREVERSE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 13923 SDValue Mask2 = Tbl2.getOperand(3); in tryToConvertShuffleOfTbl2ToTbl4() local
13925 Mask2.getOpcode() != ISD::BUILD_VECTOR) in tryToConvertShuffleOfTbl2ToTbl4()
13933 auto *C = dyn_cast<ConstantSDNode>(Mask2.getOperand(ShuffleMask[I] - 16)); in tryToConvertShuffleOfTbl2ToTbl4()
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