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Searched refs:Mask1 (Results 1 – 17 of 17) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUWaitSGPRHazards.cpp167 unsigned mergeMasks(unsigned Mask1, unsigned Mask2) { in mergeMasks() argument
170 Mask, std::min(AMDGPU::DepCtr::decodeFieldSaSdst(Mask1), in mergeMasks()
173 Mask, std::min(AMDGPU::DepCtr::decodeFieldVaVcc(Mask1), in mergeMasks()
176 Mask, std::min(AMDGPU::DepCtr::decodeFieldVmVsrc(Mask1), in mergeMasks()
179 Mask, std::min(AMDGPU::DepCtr::decodeFieldVaSdst(Mask1), in mergeMasks()
182 Mask, std::min(AMDGPU::DepCtr::decodeFieldVaVdst(Mask1), in mergeMasks()
185 Mask, std::min(AMDGPU::DepCtr::decodeFieldHoldCnt(Mask1), in mergeMasks()
188 Mask, std::min(AMDGPU::DepCtr::decodeFieldVaSsrc(Mask1), in mergeMasks()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZTDC.cpp289 int Mask0, Mask1; in convertLogicOp() local
292 std::tie(Op1, Mask1, Worthy1) = ConvertedInsts[cast<Instruction>(I.getOperand(1))]; in convertLogicOp()
298 Mask = Mask0 & Mask1; in convertLogicOp()
301 Mask = Mask0 | Mask1; in convertLogicOp()
304 Mask = Mask0 ^ Mask1; in convertLogicOp()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DEarlyCSE.cpp994 auto IsSubmask = [](const Value *Mask0, const Value *Mask1) { in isNonTargetIntrinsicMatch() argument
996 if (Mask0 == Mask1) in isNonTargetIntrinsicMatch()
998 if (isa<UndefValue>(Mask0) || isa<UndefValue>(Mask1)) in isNonTargetIntrinsicMatch()
1001 auto *Vec1 = dyn_cast<ConstantVector>(Mask1); in isNonTargetIntrinsicMatch()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSystemRegister.td62 // Mask1 Mask2 Mask3 Enc12, Name
H A DARMISelLowering.cpp6173 SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32); in LowerFCOPYSIGN() local
6175 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1); in LowerFCOPYSIGN()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineVectorOps.cpp2199 SmallVector<int, 16> Mask1; in foldSelectShuffleOfSelectShuffle() local
2200 ShufOp->getShuffleMask(Mask1); in foldSelectShuffleOfSelectShuffle()
2201 assert(Mask1.size() == NumElts && "Vector size changed with select shuffle"); in foldSelectShuffleOfSelectShuffle()
2206 ShuffleVectorInst::commuteShuffleMask(Mask1, NumElts); in foldSelectShuffleOfSelectShuffle()
2215 NewMask[i] = Mask[i] < (signed)NumElts ? Mask[i] : Mask1[i]; in foldSelectShuffleOfSelectShuffle()
H A DInstCombineCalls.cpp3164 uint64_t Mask1 = computeKnownBits(Mask, II).One.getZExtValue(); in visitCallInst() local
3166 uint64_t C = Bytes1 & Mask1; in visitCallInst()
H A DInstCombineCompares.cpp3838 APInt Mask1 = IsTrailing ? APInt::getLowBitsSet(BitWidth, Num + 1) in foldICmpEqIntrinsicWithConstant() local
3843 return new ICmpInst(Pred, Builder.CreateAnd(II->getArgOperand(0), Mask1), in foldICmpEqIntrinsicWithConstant()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DVPlanTransforms.cpp266 VPValue *Mask1 = getPredicatedMask(Region1); in mergeReplicateRegionsIntoSuccessors() local
268 if (!Mask1 || Mask1 != Mask2) in mergeReplicateRegionsIntoSuccessors()
271 assert(Mask1 && Mask2 && "both region must have conditions"); in mergeReplicateRegionsIntoSuccessors()
H A DVectorCombine.cpp1975 ArrayRef<int> Mask0, Mask1; in foldPermuteOfBinops() local
1981 m_OneUse(m_Shuffle(m_Value(Op10), m_Value(Op11), m_Mask(Mask1)))); in foldPermuteOfBinops()
2014 NewMask1.push_back(Match1 ? Mask1[M] : M); in foldPermuteOfBinops()
2037 TargetTransformInfo::SK_PermuteTwoSrc, BinOpTy, Op1Ty, Mask1, CostKind, in foldPermuteOfBinops()
/freebsd/contrib/llvm-project/clang/lib/CodeGen/TargetBuiltins/
H A DPPC.cpp391 Value *Mask1 = Builder.CreateCall(Lvs, Op0, "mask1"); in EmitPPCBuiltinExpr() local
395 Value *AllElts = Builder.CreateCall(Vperm, {Op0, Op1, Mask1}, "shuffle1"); in EmitPPCBuiltinExpr()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAGHVX.cpp2089 auto same = [](ArrayRef<int> Mask1, ArrayRef<int> Mask2) -> bool { in contracting() argument
2090 return Mask1 == Mask2; in contracting()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp10006 APInt Mask1 = APInt::getSplat(Sz, APInt(8, 0x55)); in expandBITREVERSE() local
10027 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(Mask1, dl, VT)); in expandBITREVERSE()
10028 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(Mask1, dl, VT)); in expandBITREVERSE()
10071 APInt Mask1 = APInt::getSplat(Sz, APInt(8, 0x55)); in expandVPBITREVERSE() local
10102 DAG.getConstant(Mask1, dl, VT), Mask, EVL); in expandVPBITREVERSE()
10103 Tmp3 = DAG.getNode(ISD::VP_AND, dl, VT, Tmp, DAG.getConstant(Mask1, dl, VT), in expandVPBITREVERSE()
H A DDAGCombiner.cpp8055 ConstantSDNode *Mask1 = isConstOrConstSplat(N1.getOperand(1)); in matchBSwapHWordOrAndAnd() local
8056 if (!Mask0 || !Mask1) in matchBSwapHWordOrAndAnd()
8059 Mask1->getAPIntValue() != 0x00ff00ff) in matchBSwapHWordOrAndAnd()
26066 SmallVector<int, 16> Mask1(HalfNumElts, -1); in foldShuffleOfConcatUndefs() local
26077 Mask1[i - HalfNumElts] = M; in foldShuffleOfConcatUndefs()
26085 !TLI.isShuffleMaskLegal(Mask1, HalfVT)) in foldShuffleOfConcatUndefs()
26093 SDValue Shuf1 = DAG.getVectorShuffle(HalfVT, DL, X, Y, Mask1); in foldShuffleOfConcatUndefs()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp6175 SmallVector<int, 64> Mask0, Mask1; in getFauxShuffleMask() local
6177 narrowShuffleMaskElts(MaskSize / SrcMask1.size(), SrcMask1, Mask1); in getFauxShuffleMask()
6183 if (Mask0[i] == SM_SentinelZero && Mask1[i] == SM_SentinelZero) in getFauxShuffleMask()
6185 else if (Mask1[i] == SM_SentinelZero) in getFauxShuffleMask()
41878 SmallVector<int, 32> Mask0, Mask1, ScaledMask0, ScaledMask1; in combineBlendOfPermutes() local
41880 !getTargetShuffleMask(BC1, /*AllowSentinelZero=*/false, Ops1, Mask1) || in combineBlendOfPermutes()
41882 !scaleShuffleElements(Mask1, NumElts, ScaledMask1)) in combineBlendOfPermutes()
50120 SmallVector<int> Mask0, Mask1, ScaledMask0, ScaledMask1; in combineHorizOpWithShuffle() local
50126 getTargetShuffleInputs(BC1, Ops1, Mask1, DAG) && !isAnyZero(Mask1) && in combineHorizOpWithShuffle()
50127 scaleShuffleElements(Mask1, 2, ScaledMask1) && in combineHorizOpWithShuffle()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp7605 auto Mask1 = MIRBuilder.buildConstant(S64, 0xffffffffffULL); in lowerU64ToF32BitOps() local
7606 auto T = MIRBuilder.buildAnd(S64, U, Mask1); in lowerU64ToF32BitOps()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp13922 SDValue Mask1 = Tbl1.getOperand(3); in tryToConvertShuffleOfTbl2ToTbl4() local
13924 if (Mask1.getOpcode() != ISD::BUILD_VECTOR || in tryToConvertShuffleOfTbl2ToTbl4()
13931 TBLMaskParts[I] = Mask1.getOperand(ShuffleMask[I]); in tryToConvertShuffleOfTbl2ToTbl4()