| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZTDC.cpp | 293 int Mask0, Mask1; in convertLogicOp() local
296 std::tie(Op1, Mask1, Worthy1) = ConvertedInsts[cast<Instruction>(I.getOperand(1))]; in convertLogicOp()
302 Mask = Mask0 & Mask1; in convertLogicOp()
305 Mask = Mask0 | Mask1; in convertLogicOp()
308 Mask = Mask0 ^ Mask1; in convertLogicOp()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | EarlyCSE.cpp | 1005 auto IsSubmask = [](const Value *Mask0, const Value *Mask1) { in isNonTargetIntrinsicMatch() argument
1007 if (Mask0 == Mask1) in isNonTargetIntrinsicMatch()
1009 if (isa<UndefValue>(Mask0) || isa<UndefValue>(Mask1)) in isNonTargetIntrinsicMatch()
1012 auto *Vec1 = dyn_cast<ConstantVector>(Mask1); in isNonTargetIntrinsicMatch()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VPlanTransforms.cpp | 237 VPValue *Mask1 = getPredicatedMask(Region1); in mergeReplicateRegionsIntoSuccessors() local
239 if (!Mask1 || Mask1 != Mask2) in mergeReplicateRegionsIntoSuccessors()
242 assert(Mask1 && Mask2 && "both region must have conditions"); in mergeReplicateRegionsIntoSuccessors()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMSystemRegister.td | 45 // Mask1 Mask2 Mask3 Enc12, Name
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| H A D | ARMISelLowering.cpp | 6100 SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32); in LowerFCOPYSIGN() local
6102 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1); in LowerFCOPYSIGN()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineVectorOps.cpp | 2121 SmallVector<int, 16> Mask1; in foldSelectShuffleOfSelectShuffle() local
2122 ShufOp->getShuffleMask(Mask1); in foldSelectShuffleOfSelectShuffle()
2123 assert(Mask1.size() == NumElts && "Vector size changed with select shuffle"); in foldSelectShuffleOfSelectShuffle()
2128 ShuffleVectorInst::commuteShuffleMask(Mask1, NumElts); in foldSelectShuffleOfSelectShuffle()
2137 NewMask[i] = Mask[i] < (signed)NumElts ? Mask[i] : Mask1[i]; in foldSelectShuffleOfSelectShuffle()
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| H A D | InstCombineCalls.cpp | 2869 uint64_t Mask1 = computeKnownBits(Mask, 0, II).One.getZExtValue(); in visitCallInst() local
2871 uint64_t C = Bytes1 & Mask1; in visitCallInst()
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| H A D | InstCombineCompares.cpp | 3645 APInt Mask1 = IsTrailing ? APInt::getLowBitsSet(BitWidth, Num + 1) in foldICmpEqIntrinsicWithConstant() local
3650 return new ICmpInst(Pred, Builder.CreateAnd(II->getArgOperand(0), Mask1), in foldICmpEqIntrinsicWithConstant()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAGHVX.cpp | 2098 auto same = [](ArrayRef<int> Mask1, ArrayRef<int> Mask2) -> bool { in contracting()
2099 return Mask1 == Mask2; in contracting()
2100 __anon9fc097471602(ArrayRef<int> Mask1, ArrayRef<int> Mask2) contracting() argument
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 9511 APInt Mask1 = APInt::getSplat(Sz, APInt(8, 0x55)); in expandBITREVERSE() local
9532 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(Mask1, dl, VT)); in expandBITREVERSE()
9533 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(Mask1, dl, VT)); in expandBITREVERSE()
9576 APInt Mask1 = APInt::getSplat(Sz, APInt(8, 0x55)); in expandVPBITREVERSE() local
9607 DAG.getConstant(Mask1, dl, VT), Mask, EVL); in expandVPBITREVERSE()
9608 Tmp3 = DAG.getNode(ISD::VP_AND, dl, VT, Tmp, DAG.getConstant(Mask1, dl, VT), in expandVPBITREVERSE()
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| H A D | DAGCombiner.cpp | 7595 ConstantSDNode *Mask1 = isConstOrConstSplat(N1.getOperand(1)); in matchBSwapHWordOrAndAnd() local
7596 if (!Mask0 || !Mask1) in matchBSwapHWordOrAndAnd()
7599 Mask1->getAPIntValue() != 0x00ff00ff) in matchBSwapHWordOrAndAnd()
24990 SmallVector<int, 16> Mask1(HalfNumElts, -1); in foldShuffleOfConcatUndefs() local
25001 Mask1[i - HalfNumElts] = M; in foldShuffleOfConcatUndefs()
25009 !TLI.isShuffleMaskLegal(Mask1, HalfVT)) in foldShuffleOfConcatUndefs()
25017 SDValue Shuf1 = DAG.getVectorShuffle(HalfVT, DL, X, Y, Mask1); in foldShuffleOfConcatUndefs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 5880 SmallVector<int, 64> Mask0, Mask1; in getFauxShuffleMask() local
5882 narrowShuffleMaskElts(MaskSize / SrcMask1.size(), SrcMask1, Mask1); in getFauxShuffleMask()
5888 if (Mask0[i] == SM_SentinelZero && Mask1[i] == SM_SentinelZero) in getFauxShuffleMask()
5890 else if (Mask1[i] == SM_SentinelZero) in getFauxShuffleMask()
40392 SmallVector<int, 32> Mask0, Mask1, ScaledMask0, ScaledMask1; in combineBlendOfPermutes() local
40394 !getTargetShuffleMask(BC1, /*AllowSentinelZero=*/false, Ops1, Mask1) || in combineBlendOfPermutes()
40396 !scaleShuffleElements(Mask1, NumElts, ScaledMask1)) in combineBlendOfPermutes()
48365 SmallVector<int> Mask0, Mask1, ScaledMask0, ScaledMask1; in combineHorizOpWithShuffle() local
48371 getTargetShuffleInputs(BC1, Ops1, Mask1, DAG) && !isAnyZero(Mask1) && in combineHorizOpWithShuffle()
48372 scaleShuffleElements(Mask1, 2, ScaledMask1) && in combineHorizOpWithShuffle()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 6916 auto Mask1 = MIRBuilder.buildConstant(S64, 0xffffffffffULL); in lowerU64ToF32BitOps() local
6917 auto T = MIRBuilder.buildAnd(S64, U, Mask1); in lowerU64ToF32BitOps()
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| /freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 17148 Value *Mask1 = Builder.CreateCall(Lvs, Op0, "mask1"); in EmitPPCBuiltinExpr() local
17152 Value *AllElts = Builder.CreateCall(Vperm, {Op0, Op1, Mask1}, "shuffle1"); in EmitPPCBuiltinExpr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 13092 SDValue Mask1 = Tbl1->getOperand(3); in tryToConvertShuffleOfTbl2ToTbl4() local
13097 TBLMaskParts[I] = Mask1->getOperand(ShuffleMask[I]); in tryToConvertShuffleOfTbl2ToTbl4()
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