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Searched refs:MT_DMA_SHDL (Results 1 – 4 of 4) sorted by relevance

/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Ddma.c170 mt76_rmw(dev, MT_DMA_SHDL(MT_DMASHDL_PKT_MAX_SIZE), in mt7663_dma_sched_init()
176 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_REFILL), 0xffc80000); in mt7663_dma_sched_init()
178 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_OPTIONAL), 0x70068037); in mt7663_dma_sched_init()
182 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(i)), in mt7663_dma_sched_init()
185 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(5)), in mt7663_dma_sched_init()
188 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(15)), in mt7663_dma_sched_init()
192 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(0)), 0x42104210); in mt7663_dma_sched_init()
193 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(1)), 0x42104210); in mt7663_dma_sched_init()
194 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(2)), 0x00050005); in mt7663_dma_sched_init()
195 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(3)), 0); in mt7663_dma_sched_init()
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H A Dusb_sdio.c230 mt76_rmw(dev, MT_DMA_SHDL(MT_DMASHDL_PKT_MAX_SIZE), in mt7663u_dma_sched_init()
238 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_REFILL), 0xffe00006); in mt7663u_dma_sched_init()
239 mt76_clear(dev, MT_DMA_SHDL(MT_DMASHDL_PAGE), BIT(16)); in mt7663u_dma_sched_init()
242 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(i)), in mt7663u_dma_sched_init()
246 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(0)), 0x42104210); in mt7663u_dma_sched_init()
247 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(1)), 0x42104210); in mt7663u_dma_sched_init()
249 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(2)), 0x4444); in mt7663u_dma_sched_init()
254 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_SCHED_SET0), 0x6501234f); in mt7663u_dma_sched_init()
255 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_SCHED_SET1), 0xedcba987); in mt7663u_dma_sched_init()
256 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_OPTIONAL), 0x7004801c); in mt7663u_dma_sched_init()
H A Dregs.h524 #define MT_DMA_SHDL(ofs) (dev->reg_map[MT_DMA_SHDL_BASE] + (ofs)) macro
/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt792x_regs.h398 #define MT_DMA_SHDL(ofs) (0x7c026000 + (ofs)) macro
399 #define MT_DMASHDL_SW_CONTROL MT_DMA_SHDL(0x004)
401 #define MT_DMASHDL_OPTIONAL MT_DMA_SHDL(0x008)
402 #define MT_DMASHDL_PAGE MT_DMA_SHDL(0x00c)
404 #define MT_DMASHDL_REFILL MT_DMA_SHDL(0x010)
406 #define MT_DMASHDL_PKT_MAX_SIZE MT_DMA_SHDL(0x01c)
410 #define MT_DMASHDL_GROUP_QUOTA(_n) MT_DMA_SHDL(0x020 + ((_n) << 2))
414 #define MT_DMASHDL_Q_MAP(_n) MT_DMA_SHDL(0x060 + ((_n) << 2))
418 #define MT_DMASHDL_SCHED_SET(_n) MT_DMA_SHDL(0x070 + ((_n) << 2))