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Searched refs:MSR (Results 1 – 25 of 33) sorted by relevance

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/freebsd/sys/contrib/xen/arch-x86/
H A Dcpufeatureset.h100 XEN_CPUFEATURE(MSR, 0*32+ 5) /*A Model-Specific Registers, RDMSR, WRMSR */
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64.td46 // Named operands for MRS/MSR/TLBI/...
H A DAArch64SchedFalkorDetails.td1257 def : InstRW<[FalkorWr_1SD_1ST_0cyc], (instrs MSR)>;
H A DAArch64SMEInstrInfo.td268 (MSR 0xde85, GPR64:$val)>;
H A DAArch64SchedKryoDetails.td1662 (instrs MSR)>;
H A DSMEInstrFormats.td332 // MSR SVCRSM, #<imm1>
333 // MSR SVCRZA, #<imm1>
334 // MSR SVCRSMZA, #<imm1>
H A DAArch64SchedNeoverseV1.td563 // MSR
H A DAArch64FrameLowering.cpp4674 MachineInstrs.push_back(BuildMI(MBB, MI, DL, TII->get(AArch64::MSR)) in expandFillPPRFromZPRSlotPseudo()
/freebsd/sys/dev/uart/
H A Duart_dev_ns8250.c573 #define MSR(sig) MSR_##sig macro
583 if ((msr) & MSR(sig)) { \
600 if (((msr) & MSR(sig)) != 0) \
/freebsd/sys/contrib/device-tree/src/arm/nxp/mxs/
H A Dimx28-m28cu3.dts10 model = "MSR M28CU3";
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrHTM.td91 // value of the MSR Transaction State (TS) bits that exist before the
H A DP9InstrResources.td939 (instregex "M(T|F)MSR(D)?$"),
/freebsd/share/doc/papers/
H A Dbsdreferences.bib73 series = {MSR '11},
92 series = {MSR '08},
/freebsd/contrib/processor-trace/libipt/include/
H A Dintel-pt.h.in282 * IA32_RTIT_CTL.TraceEn (MSR 570H, bit 0) while PacketEn is 1 then a
285 * VM-entry MSR-load area includes an entry for the IA32_RTIT_CTL MSR.
304 * unconditional branch clears IA32_RTIT_STATUS.FilterEn (MSR 571H, bit
317 * pair, as a result of IA32_RTIT_STATUS.FilterEn[0] (MSR 571H) being
326 * and generates an OVF (Overflow) packet just as IA32_RTIT_CTL (MSR
328 * causes IA32_RTIT_STATUS.ContextEn[1] (MSR 571H) to be cleared, the
391 * This corresponds to the respective fields in IA32_RTIT_CTL MSR.
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleM7.td401 // MSR/MRS
402 def : InstRW<[M7NonGeneralPurpose], (instregex "MSR", "MRS")>;
H A DARMScheduleM85.td520 // MSR/MRS
521 def : InstRW<[M85NonGeneralPurpose], (instregex "MSR", "MRS")>;
H A DARMScheduleR52.td343 def : InstRW<[R52WriteLd, R52Read_EX1], (instregex "MSR", "MSRbanked")>;
H A DARMScheduleA57.td134 "(t2)?MSR(banked|i|_AR|_M)?$")>;
H A DARMInstrInfo.td5861 // No need to have both system and application versions of MSR (immediate) or
5862 // MSR (register), the encodings are the same and the assembly parser has no way
5867 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
5895 // However, the MSR (banked register) system instruction (ARMv7VE) *does* have a
H A DARMInstrThumb2.td4567 // A/R class MSR.
4587 // However, the MSR (banked register) system instruction (ARMv7VE) *does* have a
4606 // M class MSR.
/freebsd/crypto/openssl/doc/man3/
H A DOPENSSL_ia32cap.pod126 =item bit #128+29 denoting support for IA32_ARCH_CAPABILITIES MSR;
/freebsd/share/misc/
H A Diso3166170 MS MSR 500 Montserrat
H A Dusb_hid_usages1721 0x01 MSR Device Read-Only
H A Dusb_vendors1010 0328 K016: USB-MSR ISO 3-track MSR: POS Standard (See HID pages)
1011 0329 K018: USB-MSR JIS 2-Track MSR: POS Standard
1012 032a K016: USB-MSR ISO 3-Track MSR: HID Keyboard Mode
1013 032b K016/K018: USB-MSR Flash-Recovery/Download
4693 4671 4820 LCD w/ MSR/KB
23449 5131 MSR
23450 2007 MSR-101U Mini HID magnetic card reader
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.td1432 def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>;

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