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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dmsi.txt1 This document describes the generic device tree binding for MSI controllers and
9 those busses to the MSI controllers which they are capable of using,
17 they can address. An MSI controller may feature a number of doorbells.
22 MSI controllers may have restrictions on permitted payloads.
28 MSI controller and device rather than a property of either in isolation).
31 MSI controllers:
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
35 address by some master. An MSI controller may feature a number of doorbells.
40 - msi-controller: Identifies the node as an MSI controller.
51 the specific MSI controller.
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H A Dfsl,ls-scfg-msi.txt1 * Freescale Layerscape SCFG PCIe MSI controller
6 Layerscape PCIe MSI controller block such as:
12 - msi-controller: indicates that this is a PCIe MSI controller node
21 MSI controller node
H A Dal,alpine-msix.txt3 See arm,gic-v3.txt for SPI and MSI definitions.
12 - al,msi-base-spi: SPI base of the MSI frame
13 - al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0
H A Dmarvell,odmi-controller.txt2 * Marvell ODMI for MSI support
5 which can be used by on-board peripheral for MSI interrupts.
15 - msi-controller : Identifies the node as an MSI controller.
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dbrcm,iproc-pcie.txt44 MSI support (optional):
46 For older platforms without MSI integrated in the GIC, iProc PCIe core provides
47 an event queue based MSI support. The iProc MSI uses host memories to store
48 MSI posted writes in the event queues
50 On newer iProc platforms, gicv2m or gicv3-its based MSI support should be used
52 - msi-map: Maps a Requester ID to an MSI controller and associated MSI
55 - msi-parent: Link to the device node of the MSI controller, used when no MSI
56 sideband data is passed between the iProc PCIe controller and the MSI
64 When the iProc event queue based MSI is used, one needs to define the
65 following properties in the MSI device node:
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H A Dpci-msi.txt2 relationship between PCI devices and MSI controllers.
18 Requester ID. A mechanism is required to associate a device with both the MSI
22 For generic MSI bindings, see
32 - msi-map: Maps a Requester ID to an MSI controller and associated
38 * msi-controller is a single phandle to an MSI controller
52 - msi-parent: Describes the MSI parent of the root complex itself. Where
53 the root complex and MSI controller do not pass sideband data with MSI
54 writes, this property may be used to describe the MSI controller(s)
79 * The sideband data provided to the MSI controller is
107 * The sideband data provided to the MSI controller is
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H A Dxgene-pci-msi.txt1 * AppliedMicro X-Gene v1 PCIe MSI controller
6 X-Gene v1 PCIe MSI controller block.
7 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
9 registers. These registers include the MSI termination address and data
10 registers as well as the MSI interrupt status registers.
16 Each PCIe node needs to have property msi-parent that points to an MSI
23 + MSI node:
46 + PCIe controller node with msi-parent property pointing to MSI node:
H A Dlayerscape-pcie-gen4.txt17 none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
19 none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
23 - msi-parent : See the generic MSI binding described in
H A Dtango-pcie.txt13 - interrupts: spec for misc interrupts, spec for MSI
28 <55 IRQ_TYPE_LEVEL_HIGH>; /* MSI */
/freebsd/contrib/llvm-project/llvm/lib/MC/MCDisassembler/
H A DDisassembler.h66 std::unique_ptr<const llvm::MCSubtargetInfo> MSI; variable
91 std::unique_ptr<const MCSubtargetInfo> &&MSI, in LLVMDisasmContext() argument
98 MAI(std::move(MAI)), MRI(std::move(MRI)), MSI(std::move(MSI)), in LLVMDisasmContext()
113 const MCSubtargetInfo *getSubtargetInfo() const { return MSI.get(); } in getSubtargetInfo()
/freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A Dmsi-pic.txt1 * Freescale MSI interrupt controller
8 version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is
17 region must be added because different MSI group has different MSIIR1 offset.
27 optional, without this, all the MSI interrupts can be used.
29 no splitting an individual MSI register or the associated PIC interrupt).
34 is used for MSI messaging. The address of MSIIR in PCI address space is
35 the MSI message address.
84 Freescale MSI driver calculates the address of MSIIR (in the MSI register
85 block) and sets that address as the MSI message address.
/freebsd/sys/contrib/device-tree/Bindings/mailbox/
H A Dbrcm,iproc-flexrm-mbox.txt14 - msi-parent: Phandles (and potential Device IDs) to MSI controllers
16 interrupts) to CPU. There is one MSI for each FlexRM ring.
23 The 2nd cell contains MSI completion threshold. This is the
25 one MSI interrupt to CPU.
27 The 3rd cell contains MSI timer value representing time for
31 specified by this cell then it will inject one MSI interrupt
/freebsd/sys/dev/cxgbe/firmware/
H A Dt4fw_cfg.txt46 # PFs 0-3. These get 8 MSI/8 MSI-X vectors each. VFs are supported by
97 # It gets 32 MSI/128 MSI-X vectors.
130 # PF5 is the SCSI Controller PF. It gets 32 MSI/40 MSI-X vectors.
136 # PF6 is the FCoE Controller PF. It gets 32 MSI/40 MSI-X vectors.
H A Dt6fw_cfg_hashfilter.txt81 # PFs 0-3. These get 8 MSI/8 MSI-X vectors each. VFs are supported by
132 # It gets 32 MSI/128 MSI-X vectors.
157 # PF5 is the SCSI Controller PF. It gets 32 MSI/40 MSI-X vectors.
163 # PF6 is the FCoE Controller PF. It gets 32 MSI/40 MSI-X vectors.
H A Dt5fw_cfg.txt90 # PFs 0-3. These get 8 MSI/8 MSI-X vectors each. VFs are supported by
141 # It gets 32 MSI/128 MSI-X vectors.
175 # PF5 is the SCSI Controller PF. It gets 32 MSI/40 MSI-X vectors.
181 # PF6 is the FCoE Controller PF. It gets 32 MSI/40 MSI-X vectors.
H A Dt5fw_cfg_hashfilter.txt99 # PFs 0-3. These get 8 MSI/8 MSI-X vectors each. VFs are supported by
150 # It gets 32 MSI/128 MSI-X vectors.
178 # PF5 is the SCSI Controller PF. It gets 32 MSI/40 MSI-X vectors.
184 # PF6 is the FCoE Controller PF. It gets 32 MSI/40 MSI-X vectors.
H A Dt6fw_cfg.txt88 # PFs 0-3. These get 8 MSI/8 MSI-X vectors each. VFs are supported by
139 # It gets 32 MSI/128 MSI-X vectors.
175 # PF5 is the SCSI Controller PF. It gets 32 MSI/40 MSI-X vectors.
181 # PF6 is the FCoE Controller PF. It gets 32 MSI/40 MSI-X vectors.
H A Dt5fw_cfg_fpga.txt26 # 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV
28 # same umber of MSI-X Vectors as the base Physical Function.
30 # not, their MSI-X "needs" are counted by the PCI-E implementation.
41 # to allow for this. And because of the MSI-X resource allocation
54 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
62 # 8 Ingress Queue/MSI-X Vectors per application function
64 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
176 # NMSIX = 1088 # available MSI-X Vectors
187 # Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
191 # Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
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H A Dt4fw_cfg_uwire.txt26 # 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV
28 # same umber of MSI-X Vectors as the base Physical Function.
30 # not, their MSI-X "needs" are counted by the PCI-E implementation.
41 # to allow for this. And because of the MSI-X resource allocation
54 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
62 # 8 Ingress Queue/MSI-X Vectors per application function
64 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
159 # NMSIX = 1088 # available MSI-X Vectors
170 # Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
174 # Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
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H A Dt6fw_cfg_fpga.txt25 # 4. MSI-X Vectors: 1088.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 16 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
188 # NMSIX = 1088 # available MSI-X Vectors
199 # Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
203 # Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
211 # NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)
218 # NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ)
225 # NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ)
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H A Dt5fw_cfg_uwire.txt25 # 4. MSI-X Vectors: 1088.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 8 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
194 # NMSIX = 1088 # available MSI-X Vectors
205 # Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
209 # Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
217 # NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)
224 # NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ)
231 # NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ)
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H A Dt6fw_cfg_uwire.txt25 # 4. MSI-X Vectors: 1088.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 16 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
211 # NMSIX = 1088 # available MSI-X Vectors
222 # Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
226 # Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
234 # NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)
241 # NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ)
248 # NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ)
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/freebsd/sys/contrib/device-tree/Bindings/powerpc/4xx/
H A Dhsta.txt10 Currently only the MSI support is used by Linux using the following
15 - reg : register mapping for the HSTA MSI space
16 - interrupts : ordered interrupt mapping for each MSI in the register
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64StackTagging.cpp158 bool addMemSet(uint64_t Offset, MemSetInst *MSI) { in addMemSet() argument
159 uint64_t StoreSize = cast<ConstantInt>(MSI->getLength())->getZExtValue(); in addMemSet()
160 if (!addRange(Offset, Offset + StoreSize, MSI)) in addMemSet()
162 IRBuilder<> IRB(MSI); in addMemSet()
164 cast<ConstantInt>(MSI->getValue())); in addMemSet()
411 MemSetInst *MSI = cast<MemSetInst>(BI); in collectInitializers() local
413 if (MSI->isVolatile() || !isa<ConstantInt>(MSI->getLength())) in collectInitializers()
416 if (!isa<ConstantInt>(MSI->getValue())) in collectInitializers()
421 MSI->getDest()->getPointerOffsetFrom(StartPtr, *DL); in collectInitializers()
425 if (!IB.addMemSet(*Offset, MSI)) in collectInitializers()
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/freebsd/sys/dev/pci/
H A Dpcib_if.m113 # Allocate 'count' MSI messages mapped onto 'count' IRQs. 'irq' points
128 # Release 'count' MSI messages mapped onto 'count' IRQs stored in the
139 # Allocate a single MSI-X message mapped onto '*irq'.
148 # Release a single MSI-X message mapped onto 'irq'.
157 # Determine the MSI/MSI-X message address and data for 'irq'. The address

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