1*c66ec88fSEmmanuel VadotAlpine MSIX controller 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel VadotSee arm,gic-v3.txt for SPI and MSI definitions. 4*c66ec88fSEmmanuel Vadot 5*c66ec88fSEmmanuel VadotRequired properties: 6*c66ec88fSEmmanuel Vadot 7*c66ec88fSEmmanuel Vadot- compatible: should be "al,alpine-msix" 8*c66ec88fSEmmanuel Vadot- reg: physical base address and size of the registers 9*c66ec88fSEmmanuel Vadot- interrupt-controller: identifies the node as an interrupt controller 10*c66ec88fSEmmanuel Vadot- msi-controller: identifies the node as an PCI Message Signaled Interrupt 11*c66ec88fSEmmanuel Vadot controller 12*c66ec88fSEmmanuel Vadot- al,msi-base-spi: SPI base of the MSI frame 13*c66ec88fSEmmanuel Vadot- al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0 14*c66ec88fSEmmanuel Vadot 15*c66ec88fSEmmanuel VadotExample: 16*c66ec88fSEmmanuel Vadot 17*c66ec88fSEmmanuel Vadotmsix: msix { 18*c66ec88fSEmmanuel Vadot compatible = "al,alpine-msix"; 19*c66ec88fSEmmanuel Vadot reg = <0x0 0xfbe00000 0x0 0x100000>; 20*c66ec88fSEmmanuel Vadot interrupt-parent = <&gic>; 21*c66ec88fSEmmanuel Vadot interrupt-controller; 22*c66ec88fSEmmanuel Vadot msi-controller; 23*c66ec88fSEmmanuel Vadot al,msi-base-spi = <160>; 24*c66ec88fSEmmanuel Vadot al,msi-num-spis = <160>; 25*c66ec88fSEmmanuel Vadot}; 26