1098ca2bdSWarner Losh#- 221c3015aSDoug Rabson# Copyright (c) 2000 Doug Rabson 321c3015aSDoug Rabson# All rights reserved. 421c3015aSDoug Rabson# 521c3015aSDoug Rabson# Redistribution and use in source and binary forms, with or without 621c3015aSDoug Rabson# modification, are permitted provided that the following conditions 721c3015aSDoug Rabson# are met: 821c3015aSDoug Rabson# 1. Redistributions of source code must retain the above copyright 921c3015aSDoug Rabson# notice, this list of conditions and the following disclaimer. 1021c3015aSDoug Rabson# 2. Redistributions in binary form must reproduce the above copyright 1121c3015aSDoug Rabson# notice, this list of conditions and the following disclaimer in the 1221c3015aSDoug Rabson# documentation and/or other materials provided with the distribution. 1321c3015aSDoug Rabson# 1421c3015aSDoug Rabson# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1521c3015aSDoug Rabson# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1621c3015aSDoug Rabson# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1721c3015aSDoug Rabson# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1821c3015aSDoug Rabson# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1921c3015aSDoug Rabson# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2021c3015aSDoug Rabson# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2121c3015aSDoug Rabson# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2221c3015aSDoug Rabson# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2321c3015aSDoug Rabson# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2421c3015aSDoug Rabson# SUCH DAMAGE. 2521c3015aSDoug Rabson# 2621c3015aSDoug Rabson# 2721c3015aSDoug Rabson 2821c3015aSDoug Rabson#include <sys/bus.h> 2955d3ea17SRyan Stone#include <sys/rman.h> 30283f4553SWarner Losh#include <dev/pci/pcivar.h> 3155d3ea17SRyan Stone#include <dev/pci/pcib_private.h> 3221c3015aSDoug Rabson 3321c3015aSDoug RabsonINTERFACE pcib; 3421c3015aSDoug Rabson 35491bfec7SWarner LoshCODE { 36491bfec7SWarner Losh static int 37491bfec7SWarner Losh null_route_interrupt(device_t pcib, device_t dev, int pin) 38491bfec7SWarner Losh { 39491bfec7SWarner Losh return (PCI_INVALID_IRQ); 40491bfec7SWarner Losh } 412397d2d8SRyan Stone 422397d2d8SRyan Stone static int 432397d2d8SRyan Stone pcib_null_ari_enabled(device_t pcib) 442397d2d8SRyan Stone { 452397d2d8SRyan Stone 462397d2d8SRyan Stone return (0); 472397d2d8SRyan Stone } 48491bfec7SWarner Losh}; 49491bfec7SWarner Losh 50d7be980dSAndrew TurnerHEADER { 51d7be980dSAndrew Turner #include "pci_if.h" 52d7be980dSAndrew Turner}; 53d7be980dSAndrew Turner 5421c3015aSDoug Rabson# 5521c3015aSDoug Rabson# Return the number of slots on the attached PCI bus. 5621c3015aSDoug Rabson# 5721c3015aSDoug RabsonMETHOD int maxslots { 5821c3015aSDoug Rabson device_t dev; 5921c3015aSDoug Rabson}; 6021c3015aSDoug Rabson 6121c3015aSDoug Rabson# 6255d3ea17SRyan Stone# 6355d3ea17SRyan Stone# Return the number of functions on the attached PCI bus. 6455d3ea17SRyan Stone# 6555d3ea17SRyan StoneMETHOD int maxfuncs { 6655d3ea17SRyan Stone device_t dev; 6755d3ea17SRyan Stone} DEFAULT pcib_maxfuncs; 6855d3ea17SRyan Stone 6955d3ea17SRyan Stone# 7021c3015aSDoug Rabson# Read configuration space on the PCI bus. The bus, slot and func 7121c3015aSDoug Rabson# arguments determine the device which is being read and the reg 7221c3015aSDoug Rabson# argument is a byte offset into configuration space for that 7321c3015aSDoug Rabson# device. The width argument (which should be 1, 2 or 4) specifies how 7421c3015aSDoug Rabson# many byte of configuration space to read from that offset. 7521c3015aSDoug Rabson# 7621c3015aSDoug RabsonMETHOD u_int32_t read_config { 7721c3015aSDoug Rabson device_t dev; 78689634a3SAndrew Gallatin u_int bus; 79689634a3SAndrew Gallatin u_int slot; 80689634a3SAndrew Gallatin u_int func; 81689634a3SAndrew Gallatin u_int reg; 8221c3015aSDoug Rabson int width; 8321c3015aSDoug Rabson}; 8421c3015aSDoug Rabson 8521c3015aSDoug Rabson# 8621c3015aSDoug Rabson# Write configuration space on the PCI bus. The bus, slot and func 8721c3015aSDoug Rabson# arguments determine the device which is being written and the reg 8821c3015aSDoug Rabson# argument is a byte offset into configuration space for that 8921c3015aSDoug Rabson# device. The value field is written to the configuration space, with 9021c3015aSDoug Rabson# the number of bytes written depending on the width argument. 9121c3015aSDoug Rabson# 9221c3015aSDoug RabsonMETHOD void write_config { 9321c3015aSDoug Rabson device_t dev; 94689634a3SAndrew Gallatin u_int bus; 95689634a3SAndrew Gallatin u_int slot; 96689634a3SAndrew Gallatin u_int func; 97689634a3SAndrew Gallatin u_int reg; 9821c3015aSDoug Rabson u_int32_t value; 9921c3015aSDoug Rabson int width; 10021c3015aSDoug Rabson}; 1018302c166SWarner Losh 1028302c166SWarner Losh# 1038302c166SWarner Losh# Route an interrupt. Returns a value suitable for stuffing into 1048302c166SWarner Losh# a device's interrupt register. 1058302c166SWarner Losh# 1068302c166SWarner LoshMETHOD int route_interrupt { 1072961fc5aSMike Smith device_t pcib; 1088302c166SWarner Losh device_t dev; 1098302c166SWarner Losh int pin; 110283f4553SWarner Losh} DEFAULT null_route_interrupt; 1119bf4c9c1SJohn Baldwin 1129bf4c9c1SJohn Baldwin# 113*fb69997dSJose Luis Duran# Allocate 'count' MSI messages mapped onto 'count' IRQs. 'irq' points 1149bf4c9c1SJohn Baldwin# to an array of at least 'count' ints. The max number of messages this 1159bf4c9c1SJohn Baldwin# device supports is included so that the MD code can take that into 1169bf4c9c1SJohn Baldwin# account when assigning resources so that the proper number of low bits 1179bf4c9c1SJohn Baldwin# are clear in the resulting message data value. 1189bf4c9c1SJohn Baldwin# 1199bf4c9c1SJohn BaldwinMETHOD int alloc_msi { 1209bf4c9c1SJohn Baldwin device_t pcib; 1219bf4c9c1SJohn Baldwin device_t dev; 1229bf4c9c1SJohn Baldwin int count; 1239bf4c9c1SJohn Baldwin int maxcount; 1249bf4c9c1SJohn Baldwin int *irqs; 1259bf4c9c1SJohn Baldwin}; 1269bf4c9c1SJohn Baldwin 1279bf4c9c1SJohn Baldwin# 128e706f7f0SJohn Baldwin# Release 'count' MSI messages mapped onto 'count' IRQs stored in the 129e706f7f0SJohn Baldwin# array pointed to by 'irqs'. 1309bf4c9c1SJohn Baldwin# 1319bf4c9c1SJohn BaldwinMETHOD int release_msi { 1329bf4c9c1SJohn Baldwin device_t pcib; 1339bf4c9c1SJohn Baldwin device_t dev; 1349bf4c9c1SJohn Baldwin int count; 1359bf4c9c1SJohn Baldwin int *irqs; 1369bf4c9c1SJohn Baldwin}; 1379bf4c9c1SJohn Baldwin 1389bf4c9c1SJohn Baldwin# 1399bf4c9c1SJohn Baldwin# Allocate a single MSI-X message mapped onto '*irq'. 1409bf4c9c1SJohn Baldwin# 1419bf4c9c1SJohn BaldwinMETHOD int alloc_msix { 1429bf4c9c1SJohn Baldwin device_t pcib; 1439bf4c9c1SJohn Baldwin device_t dev; 1449bf4c9c1SJohn Baldwin int *irq; 1459bf4c9c1SJohn Baldwin}; 1469bf4c9c1SJohn Baldwin 1479bf4c9c1SJohn Baldwin# 1489bf4c9c1SJohn Baldwin# Release a single MSI-X message mapped onto 'irq'. 1499bf4c9c1SJohn Baldwin# 1509bf4c9c1SJohn BaldwinMETHOD int release_msix { 1519bf4c9c1SJohn Baldwin device_t pcib; 1529bf4c9c1SJohn Baldwin device_t dev; 1539bf4c9c1SJohn Baldwin int irq; 1549bf4c9c1SJohn Baldwin}; 155e706f7f0SJohn Baldwin 156e706f7f0SJohn Baldwin# 157e706f7f0SJohn Baldwin# Determine the MSI/MSI-X message address and data for 'irq'. The address 158e706f7f0SJohn Baldwin# is returned in '*addr', and the data in '*data'. 159e706f7f0SJohn Baldwin# 160e706f7f0SJohn BaldwinMETHOD int map_msi { 161e706f7f0SJohn Baldwin device_t pcib; 162e706f7f0SJohn Baldwin device_t dev; 163e706f7f0SJohn Baldwin int irq; 164e706f7f0SJohn Baldwin uint64_t *addr; 165e706f7f0SJohn Baldwin uint32_t *data; 166e706f7f0SJohn Baldwin}; 16762508c53SJohn Baldwin 16862508c53SJohn Baldwin# 16962508c53SJohn Baldwin# Return the device power state to be used during a system sleep state 17062508c53SJohn Baldwin# transition such as suspend and resume. 17162508c53SJohn Baldwin# 17262508c53SJohn BaldwinMETHOD int power_for_sleep { 17362508c53SJohn Baldwin device_t pcib; 17462508c53SJohn Baldwin device_t dev; 17562508c53SJohn Baldwin int *pstate; 17662508c53SJohn Baldwin}; 1775605a99eSRyan Stone 1785605a99eSRyan Stone# 1795605a99eSRyan Stone# Return the PCI Routing Identifier (RID) for the device. 1805605a99eSRyan Stone# 181d7be980dSAndrew TurnerMETHOD int get_id { 1825605a99eSRyan Stone device_t pcib; 1835605a99eSRyan Stone device_t dev; 184d7be980dSAndrew Turner enum pci_id_type type; 185d7be980dSAndrew Turner uintptr_t *id; 186d7be980dSAndrew Turner} DEFAULT pcib_get_id; 18755d3ea17SRyan Stone 18855d3ea17SRyan Stone# 18955d3ea17SRyan Stone# Enable Alternative RID Interpretation if both the downstream port (pcib) 19055d3ea17SRyan Stone# and the endpoint device (dev) both support it. 19155d3ea17SRyan Stone# 19255d3ea17SRyan StoneMETHOD int try_enable_ari { 19355d3ea17SRyan Stone device_t pcib; 19455d3ea17SRyan Stone device_t dev; 1955605a99eSRyan Stone}; 1965605a99eSRyan Stone 1972397d2d8SRyan Stone# 1982397d2d8SRyan Stone# Return non-zero if PCI ARI is enabled, or zero otherwise 1992397d2d8SRyan Stone# 2002397d2d8SRyan StoneMETHOD int ari_enabled { 2012397d2d8SRyan Stone device_t pcib; 2022397d2d8SRyan Stone} DEFAULT pcib_null_ari_enabled; 2032397d2d8SRyan Stone 2042397d2d8SRyan Stone# 2052397d2d8SRyan Stone# Decode a PCI Routing Identifier (RID) into PCI bus/slot/function 2062397d2d8SRyan Stone# 2072397d2d8SRyan StoneMETHOD void decode_rid { 2082397d2d8SRyan Stone device_t pcib; 2092397d2d8SRyan Stone uint16_t rid; 2102397d2d8SRyan Stone int *bus; 2112397d2d8SRyan Stone int *slot; 2122397d2d8SRyan Stone int *func; 2132397d2d8SRyan Stone} DEFAULT pcib_decode_rid; 2144cb67729SWarner Losh 2154cb67729SWarner Losh# 2164cb67729SWarner Losh# Request control of PCI features from host firmware, if any. 2174cb67729SWarner Losh# 2184cb67729SWarner LoshMETHOD int request_feature { 2194cb67729SWarner Losh device_t pcib; 2204cb67729SWarner Losh device_t dev; 2214cb67729SWarner Losh enum pci_feature feature; 2224cb67729SWarner Losh}; 223