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Searched refs:MRMSrcReg (Results 1 – 23 of 23) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrExtension.td39 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
47 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8:$src),
55 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
65 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
73 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
81 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
94 def MOVSX16rr16: I<0xBF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
97 def MOVZX16rr16: I<0xB7, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
114 def MOVZX32rr8_NOREX : I<0xB6, MRMSrcReg,
124 def MOVSX32rr8_NOREX : I<0xBE, MRMSrcReg,
[all …]
H A DX86InstrMMX.td37 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
55 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
76 def rr : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
93 def rr : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst),
110 def rri : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
126 def rr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
137 def rr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst),
161 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
184 def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
201 def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (out
[all...]
H A DX86InstrSSE.td26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
49 def rr_Int : SI_Int<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
72 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
95 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
197 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
342 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
821 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
828 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
836 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
843 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
[all …]
H A DX86InstrXOP.td14 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
45 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
56 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
67 def Yrr : IXOP<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
118 def rr_REV : IXOP<opc, MRMSrcReg, (outs VR128:$dst),
142 def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
171 def rr : IXOPi8Reg<opc, MRMSrcReg, (outs VR128:$dst),
248 def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
284 def rrr : IXOPi8Reg<opc, MRMSrcReg, (outs VR128:$dst),
331 def rrr : IXOPi8Reg<opc, MRMSrcReg, (out
[all...]
H A DX86InstrSystem.td34 def UD1Wr : I<0xB9, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
36 def UD1Lr : I<0xB9, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
38 def UD1Qr : RI<0xB9, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
141 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
144 def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
160 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
163 def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
206 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
208 def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
210 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
[all …]
H A DX86InstrFMA.td39 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
60 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
80 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
181 def r : FMA3S<opc, MRMSrcReg, (outs RC:$dst),
202 def r : FMA3S<opc, MRMSrcReg, (outs RC:$dst),
222 def r : FMA3S<opc, MRMSrcReg, (outs RC:$dst),
272 def r_Int : FMA3S_Int<opc, MRMSrcReg, (outs RC:$dst),
422 def rr_REV : FMA4S<opc, MRMSrcReg, (outs RC:$dst),
457 def rr_Int_REV : FMA4S_Int<opc, MRMSrcReg, (outs VR128:$dst),
526 def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
[all …]
H A DX86InstrConditionalCompare.td44 def CCMP8rr_REV : Ccmp<0x3a, MRMSrcReg, Xi8, GR8, GR8>;
45 def CCMP16rr_REV: Ccmp<0x3b, MRMSrcReg, Xi16, GR16, GR16>, PD;
46 def CCMP32rr_REV: Ccmp<0x3b, MRMSrcReg, Xi32, GR32, GR32>;
47 def CCMP64rr_REV: Ccmp<0x3b, MRMSrcReg, Xi64, GR64, GR64>;
H A DX86InstrKL.td18 : I<opcode, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), m#"\t{$src, $dst|$dst, $src}", []>,
46 def LOADIWKEY : I<0xDC, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
H A DX86Instr3DNow.td32 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn,
44 def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src), Mn,
H A DX86InstrVMX.td69 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
71 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
H A DX86InstrAVX512.td371 defm rr : AVX512_maskable_split<Opcode, MRMSrcReg, To, (outs To.RC:$dst),
652 def VINSERTPSZrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
1047 def rr : AVX512PI<opc, MRMSrcReg, (outs MaskInfo.RC:$dst), (ins SrcInfo.RC:$src),
1055 def rrkz : AVX512PI<opc, MRMSrcReg, (outs MaskInfo.RC:$dst),
1068 def rrk : AVX512PI<opc, MRMSrcReg, (outs MaskInfo.RC:$dst),
1183 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
1195 defm rr : AVX512_maskable_custom<opc, MRMSrcReg,
1587 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.RC:$dst), (ins KRC:$src),
1615 defm rr: AVX512_maskable_3src_cast<opc, MRMSrcReg, _, IdxVT, (outs _.RC:$dst),
1737 defm rr: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
[all …]
H A DX86InstrMisc.td251 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
259 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
267 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
276 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
284 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
292 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
539 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
541 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
543 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
545 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
[all …]
H A DX86InstrArithmetic.td199 let Form = MRMSrcReg;
206 let Form = MRMSrcReg;
263 : BinOpRI8<0x6B, "imul", binop_ndd_args, t, MRMSrcReg,
268 : BinOpRI<0x69, "imul", binop_ndd_args, t, MRMSrcReg,
273 : BinOpRI<0x69, "imul", binop_ndd_args, t, MRMSrcReg,
340 : BinOpRI8<0x6B, "imulzu", binop_ndd_args, t, MRMSrcReg,
345 : BinOpRI<0x69, "imulzu", binop_ndd_args, t, MRMSrcReg,
1362 def rr#suffix : ITy<0xF2, MRMSrcReg, t, (outs t.RegClass:$dst),
1410 def rr : ITy<0xF6, MRMSrcReg, t, (outs t.RegClass:$dst1, t.RegClass:$dst2),
1419 def rr_EVEX : ITy<0xF6, MRMSrcReg, t,
[all …]
H A DX86InstrTBM.td23 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl),
H A DX86InstrFormats.td48 def MRMSrcReg : Format<41>;
H A DX86InstrUtils.td987 let Form = MRMSrcReg;
996 let Form = MRMSrcReg;
1007 let Form = MRMSrcReg;
1021 let Form = MRMSrcReg;
H A DX86InstrShiftRotate.td542 : ITy<0xF0, MRMSrcReg, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1, u8imm:$src2),
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DX86RecognizableInstr.h131 MRMSrcReg = 41, enumerator
H A DX86FoldTablesEmitter.cpp267 case X86Local::MRMSrcReg: in mayFoldFromForm()
316 case X86Local::MRMSrcReg: in mayFoldFromLeftToRight()
H A DX86RecognizableInstr.cpp140 (Form == X86Local::MRMDestReg || Form == X86Local::MRMSrcReg); in RecognizableInstrBase()
622 case X86Local::MRMSrcReg: in emitInstructionSpecifier()
893 case X86Local::MRMSrcReg: in emitDecodePath()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86BaseInfo.h589 MRMSrcReg = 41, enumerator
1050 case X86II::MRMSrcReg: in getMemoryOperandNo()
H A DX86MCCodeEmitter.cpp1190 case X86II::MRMSrcReg: { in emitVEXOpcodePrefix()
1389 case X86II::MRMSrcReg: in emitREXPrefix()
1706 case X86II::MRMSrcReg: { in encodeInstruction()
H A DX86EncodingOptimization.cpp40 (TSFlags & X86II::FormMask) != X86II::MRMSrcReg || in optimizeInstFromVEX3ToVEX2()