Lines Matching refs:MRMSrcReg
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
49 def rr_Int : SI_Int<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
72 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
95 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
197 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
342 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
821 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
828 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
836 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
843 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
861 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
876 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src), asm,
891 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1042 def rr_Int : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1058 def rr_Int : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1289 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1307 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1319 def VCVTSD2SSrr_Int: I<0x5A, MRMSrcReg,
1334 def CVTSD2SSrr_Int: I<0x5A, MRMSrcReg,
1353 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1373 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1386 def VCVTSS2SDrr_Int: I<0x5A, MRMSrcReg,
1398 def CVTSS2SDrr_Int: I<0x5A, MRMSrcReg,
1527 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1536 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1547 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1562 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1576 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1612 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1622 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1632 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1645 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1662 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1674 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1698 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1712 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1720 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
1731 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1752 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1763 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
1779 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1803 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1812 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1827 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1846 def rri_Int : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
1860 def rri : SIi8<0xC2, MRMSrcReg,
1900 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
1920 def rr_Int: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
1982 def rri : PIi8<0xC2, MRMSrcReg,
2081 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2126 def rr : PI<opc, MRMSrcReg,
2216 def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),
2268 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2852 def r : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1),
2865 def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2917 def r : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2926 def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst),
2961 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2971 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2983 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2997 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3007 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3019 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3295 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3298 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3301 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3304 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3371 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3374 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3479 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3587 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3717 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
3735 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
3753 def ri : Ii8<0x70, MRMSrcReg,
3788 def rr : PDI<opc, MRMSrcReg,
3813 def rr : SS48I<opc, MRMSrcReg,
3889 def rr : PDI<opc, MRMSrcReg,
3992 def rr : Ii8<0xC4, MRMSrcReg,
4015 def VPEXTRWrr : Ii8<0xC5, MRMSrcReg,
4021 def PEXTRWrr : PDIi8<0xC5, MRMSrcReg,
4057 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4064 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4071 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),
4087 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4093 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4100 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4104 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4118 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4128 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4138 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4143 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4153 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4163 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4173 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4178 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4382 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4386 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4421 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4485 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4499 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4558 def rr : I<0xD0, MRMSrcReg,
4612 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4632 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4693 def rr : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4710 def Yrr : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
4762 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
4784 def rr : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4805 def Yrr : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
4948 def rri : SS3AI<0x0F, MRMSrcReg, (outs RC:$dst),
5013 def rr : SS48I<opc, MRMSrcReg, (outs OutRC:$dst), (ins InRC:$src),
5362 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5393 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5419 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5450 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5491 def ri : SS4AIi8<opc, MRMSrcReg,
5512 def SSri : SS4AIi8<opcss, MRMSrcReg,
5527 def SDri : SS4AIi8<opcsd, MRMSrcReg,
5546 def SSri : SS4AIi8<opcss, MRMSrcReg,
5561 def SDri : SS4AIi8<opcsd, MRMSrcReg,
5583 def SSri_Int : SS4AIi8<opcss, MRMSrcReg,
5606 def SDri_Int : SS4AIi8<opcsd, MRMSrcReg,
5714 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
5724 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
5736 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
5761 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
5827 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5856 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
5989 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6016 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6173 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6319 def rrr : Ii8Reg<opc, MRMSrcReg, (outs RC:$dst),
6452 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6578 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
6614 def rri : SS42AI<0x62, MRMSrcReg, (outs),
6632 def rri : SS42AI<0x60, MRMSrcReg, (outs),
6650 def rri : SS42AI<0x63, MRMSrcReg, (outs),
6668 def rri : SS42AI<0x61, MRMSrcReg, (outs),
6695 : ITy<0xF1, MRMSrcReg, t, (outs rc:$dst), (ins rc:$src1, t.RegClass:$src2),
6743 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
6767 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
6813 def rr : AES8I<opc, MRMSrcReg, (outs RC:$dst),
6864 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
6876 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
6889 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
6902 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
6929 def PCLMULQDQrri : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
6966 def rri : PCLMULIi8<0x44, MRMSrcReg, (outs RC:$dst),
7031 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7038 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7044 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7093 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7167 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7210 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7357 def rr : AVX8I<opc, MRMSrcReg, (outs VR128:$dst),
7374 def Yrr : AVX8I<opc, MRMSrcReg, (outs VR256:$dst),
7422 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7434 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7491 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7554 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7648 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7658 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
7810 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7836 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
7864 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
7886 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8014 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8028 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8114 def rr : PDI<0xCF, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), "",
8132 def rri : Ii8<Op, MRMSrcReg, (outs RC:$dst),
8185 def rr : AVX8I<opc, MRMSrcReg, (outs VR128:$dst),
8199 def Yrr : AVX8I<opc, MRMSrcReg, (outs VR256:$dst),
8225 def rr : I<Opc, MRMSrcReg, (outs RC:$dst),
8293 def rr : I<0x72, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
8301 def Yrr : I<0x72, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
8343 def VSHA512MSG1rr : I<0xcc, MRMSrcReg, (outs VR256:$dst),
8349 def VSHA512MSG2rr : I<0xcd, MRMSrcReg, (outs VR256:$dst),
8355 def VSHA512RNDS2rr : I<0xcb, MRMSrcReg, (outs VR256:$dst),
8366 def rr : I<0xda, MRMSrcReg, (outs VR128:$dst),
8383 def rr : Ii8<0xde, MRMSrcReg, (outs VR128:$dst),
8408 def rr : I<0xda, MRMSrcReg, (outs RC:$dst),
8431 def rr : I<opc, MRMSrcReg, (outs VR128:$dst),
8448 def Yrr : I<opc, MRMSrcReg, (outs VR256:$dst),