| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFeatures.td | 308 // Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions.
312 "Expand VFP/NEON MLA/MLS instructions">;
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| H A D | ARMScheduleR52.td | 271 (instregex "MLA", "MLS", "SMMLA", "SMMLAR", "SMMLS", "SMMLSR",
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| H A D | ARMScheduleSwift.td | 246 (instregex "MLA", "MLS", "SMMLA", "SMMLAR", "SMMLS", "SMMLSR",
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| H A D | ARMScheduleA57.td | 267 // Multiply accumulate: MLA, MLS, SMLABB, SMLABT, SMLATB, SMLATT, SMLAWB,
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| H A D | ARMScheduleA9.td | 2548 (instregex "MUL", "MULv5", "SMMUL", "SMMULR", "MLA", "MLAv5", "MLS",
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| H A D | ARMInstrInfo.td | 4365 def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd),
4380 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>,
6477 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | SMEInstrFormats.td | 2778 // SME2 Dot Products and MLA
3148 // SME2 multi-vec indexed long long MLA one source 32-bit
3183 // SME2 multi-vec indexed long long MLA one source 64-bit
3244 //SME2 multi-vec indexed long long MLA two sources 32-bit
3261 // SME2 multi-vec indexed long long MLA four sources 32-bit
3304 // SME2 multi-vec indexed long long MLA two sources 64-bit
3320 // SME2 multi-vec indexed long long MLA four sources 64-bit
3405 //SME2 single-multi long long MLA two and four sources
3437 // SME2 multiple vectors long long MLA two sources
3481 // SME2 multiple vectors long long MLA four sources
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| H A D | AArch64SchedOryon.td | 1487 "^(S|U|SQ)(MLA|MSL|MUL)(L|L2)v")>;
1521 "^SQRD(MLA|MLS|MUL)Hv")>;
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| H A D | AArch64SchedCyclone.td | 529 (instregex "MLA","MLS","SMLAL","SMLSL","UMLAL","UMLSL",
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| H A D | AArch64SchedKryoDetails.td | 1606 (instregex "(MLA|MLS|MUL)(v8i8|v4i16|v2i32)(_indexed)?")>;
1612 (instregex "(MLA|MLS|MUL|SQR?DMULH)(v16i8|v8i16|v4i32)(_indexed)?")>;
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| H A D | AArch64SchedA64FX.td | 2086 (instregex "^FABD_Z", "^F(ADD|SUBR?)_.*Z_", "^FN?(MAD|MLA|MLS|MSB)_ZP",
2117 def : InstRW<[A64FXWrite_FMAIndexed], (instregex "^F(MLA|MLS|MUL)_ZZZI")>;
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| H A D | AArch64TargetTransformInfo.cpp | 2248 if (auto MLA = instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_mul, in instCombineSVEVectorAdd() local
2251 return MLA; in instCombineSVEVectorAdd()
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| H A D | AArch64InstrInfo.td | 6011 // MLA and MLS are generated in MachineCombine
6012 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla", null_frag>;
8330 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla", null_frag>;
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| H A D | SVEInstrFormats.td | 3589 //class for generating pseudo for SVE MLA/MAD/MLS/MSB
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| H A D | AArch64InstrFormats.td | 11737 // ARMv8.3 Complex ADD/MLA instructions
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | IntrinsicsAArch64.td | 2695 // SVE2 MLA LANE.
2715 // SVE2 MLA Unpredicated.
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| /freebsd/contrib/llvm-project/clang/include/clang/Basic/ |
| H A D | arm_neon.td | 826 def MLA : IOpInst<"vmla", "....", "dQd", OP_MLA>;
843 // MUL, MLA, MLS, FMA, FMS definitions with scalar argument
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 18491 SDValue MLA; in visitFREM() local
18493 MLA = DAG.getNode(ISD::FMA, DL, VT, DAG.getNode(ISD::FNEG, DL, VT, Rnd), in visitFREM()
18497 MLA = DAG.getNode(ISD::FSUB, DL, VT, N0, Mul); in visitFREM()
18499 return NeedsCopySign ? DAG.getNode(ISD::FCOPYSIGN, DL, VT, MLA, N0) : MLA; in visitFREM()
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