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Searched refs:MCSchedModel (Results 1 – 25 of 50) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/MC/
H A DMCSchedule.cpp23 static_assert(std::is_trivial_v<MCSchedModel>,
25 const MCSchedModel MCSchedModel::Default = {DefaultIssueWidth,
43 int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI, in computeInstrLatency()
59 int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI, in computeInstrLatency()
65 return MCSchedModel::computeInstrLatency(STI, SCDesc); in computeInstrLatency()
70 int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI, in computeInstrLatency()
73 return MCSchedModel::computeInstrLatency<MCSubtargetInfo, MCInstrInfo, in computeInstrLatency()
98 MCSchedModel::getReciprocalThroughput(const MCSubtargetInfo &STI, in getReciprocalThroughput()
101 const MCSchedModel &SM = STI.getSchedModel(); in getReciprocalThroughput()
123 MCSchedModel::getReciprocalThroughput(const MCSubtargetInfo &STI, in getReciprocalThroughput()
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H A DMCSubtargetInfo.cpp239 CPUSchedModel = &MCSchedModel::Default; in InitMCProcessorInfo()
335 const MCSchedModel &MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const { in getSchedModelForCPU()
347 return MCSchedModel::Default; in getSchedModelForCPU()
355 const MCSchedModel &SchedModel = getSchedModelForCPU(CPU); in getInstrItineraryForCPU()
/freebsd/contrib/llvm-project/llvm/tools/llvm-mca/Views/
H A DInstructionInfoView.cpp61 const MCSchedModel &SM = getSubTargetInfo().getSchedModel(); in printView()
191 const MCSchedModel &SM = STI.getSchedModel(); in collectData()
213 IIVDEntry.Latency = MCSchedModel::computeInstrLatency(STI, SCDesc); in collectData()
215 IIVDEntry.Latency += MCSchedModel::getForwardingDelayCycles( in collectData()
217 IIVDEntry.RThroughput = MCSchedModel::getReciprocalThroughput(STI, SCDesc); in collectData()
225 IIVDEntry.Latency - MCSchedModel::getBypassDelayCycles(STI, SCDesc); in collectData()
H A DSummaryView.h40 const llvm::MCSchedModel &SM;
77 SummaryView(const llvm::MCSchedModel &Model, llvm::ArrayRef<llvm::MCInst> S,
H A DResourcePressureView.cpp27 const MCSchedModel &SM = getSubTargetInfo().getSchedModel(); in ResourcePressureView()
88 const MCSchedModel &SM) { in printColumnNames()
128 const MCSchedModel &SM = getSubTargetInfo().getSchedModel(); in printResourcePressurePerIter()
H A DRetireControlUnitStatistics.h50 RetireControlUnitStatistics(const MCSchedModel &SM);
H A DBottleneckAnalysis.h97 const MCSchedModel &SM;
139 PressureTracker(const MCSchedModel &Model);
H A DSchedulerStatistics.h48 const llvm::MCSchedModel &SM;
H A DRetireControlUnitStatistics.cpp20 RetireControlUnitStatistics::RetireControlUnitStatistics(const MCSchedModel &SM) in RetireControlUnitStatistics()
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/Stages/
H A DInstructionTables.h30 const MCSchedModel &SM;
35 InstructionTables(const MCSchedModel &Model) in InstructionTables()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetSchedule.h34 MCSchedModel SchedModel;
60 TargetSchedModel() : SchedModel(MCSchedModel::Default) {} in TargetSchedModel()
87 const MCSchedModel *getMCSchedModel() const { return &SchedModel; } in getMCSchedModel()
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCSubtargetInfo.h60 const MCSchedModel *SchedModel;
89 const MCSchedModel *CPUSchedModel;
163 const MCSchedModel &getSchedModelForCPU(StringRef CPU) const;
166 const MCSchedModel &getSchedModel() const { return *CPUSchedModel; } in getSchedModel()
H A DMCInstrItineraries.h112 MCSchedModel SchedModel =
113 MCSchedModel::Default; ///< Basic machine properties.
121 InstrItineraryData(const MCSchedModel &SM, const InstrStage *S, in InstrItineraryData()
H A DMCSchedule.h258 struct MCSchedModel { struct
424 LLVM_ABI static const MCSchedModel Default; argument
433 int MCSchedModel::computeInstrLatency( in computeInstrLatency()
472 return MCSchedModel::computeInstrLatency(STI, *SCDesc); in computeInstrLatency()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetSchedule.cpp238 return capLatency(MCSchedModel::computeInstrLatency(*STI, SCDesc)); in computeInstrLatency()
309 return MCSchedModel::getReciprocalThroughput(SchedClass, in computeReciprocalThroughput()
314 return MCSchedModel::getReciprocalThroughput(*STI, *resolveSchedClass(MI)); in computeReciprocalThroughput()
323 return MCSchedModel::getReciprocalThroughput(SchedClass, in computeReciprocalThroughput()
328 return MCSchedModel::getReciprocalThroughput(*STI, SCDesc); in computeReciprocalThroughput()
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/
H A DSupport.h96 LLVM_ABI void computeProcResourceMasks(const MCSchedModel &SM,
110 LLVM_ABI double computeBlockRThroughput(const MCSchedModel &SM,
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/
H A DLSUnit.h57 LSUnitBase(const MCSchedModel &SM, unsigned LoadQueueSize,
411 LSUnit(const MCSchedModel &SM) in LSUnit()
413 LSUnit(const MCSchedModel &SM, unsigned LQ, unsigned SQ) in LSUnit()
415 LSUnit(const MCSchedModel &SM, unsigned LQ, unsigned SQ, bool AssumeNoAlias) in LSUnit()
H A DRegisterFile.h229 void initialize(const MCSchedModel &SM, unsigned NumRegs);
232 RegisterFile(const MCSchedModel &SM, const MCRegisterInfo &mri,
H A DScheduler.h158 Scheduler(const MCSchedModel &Model, LSUnitBase &Lsu) in Scheduler()
161 Scheduler(const MCSchedModel &Model, LSUnitBase &Lsu, in Scheduler()
H A DRetireControlUnit.h80 RetireControlUnit(const MCSchedModel &SM);
/freebsd/contrib/llvm-project/llvm/lib/MCA/
H A DSupport.cpp40 void computeProcResourceMasks(const MCSchedModel &SM, in computeProcResourceMasks()
83 double computeBlockRThroughput(const MCSchedModel &SM, unsigned DispatchWidth, in computeBlockRThroughput()
H A DContext.cpp34 const MCSchedModel &SM = STI.getSchedModel(); in createDefaultPipeline()
75 const MCSchedModel &SM = STI.getSchedModel(); in createInOrderPipeline()
H A DInstrBuilder.cpp38 const MCSchedModel &SM = STI.getSchedModel(); in InstrBuilder()
47 const MCSchedModel &SM = STI.getSchedModel(); in initializeUsedResources()
233 int Latency = MCSchedModel::computeInstrLatency(STI, SCDesc); in computeMaxLatency()
271 const MCSchedModel &SM = STI.getSchedModel(); in populateWrites()
545 const MCSchedModel &SM = STI.getSchedModel(); in getVariantSchedClassID()
568 const MCSchedModel &SM = STI.getSchedModel(); in createInstrDescImpl()
/freebsd/contrib/llvm-project/llvm/tools/llvm-mca/
H A DPipelinePrinter.cpp52 const MCSchedModel &SM = STI.getSchedModel(); in getJSONSimulationParameters()
82 const MCSchedModel &SM = STI.getSchedModel(); in getJSONTargetInfo()
/freebsd/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp69 RegisterFile::RegisterFile(const MCSchedModel &SM, const MCRegisterInfo &mri, in RegisterFile()
77 void RegisterFile::initialize(const MCSchedModel &SM, unsigned NumRegs) { in initialize()
515 const MCSchedModel &SM = STI.getSchedModel(); in collectWrites()
582 const MCSchedModel &SM = STI.getSchedModel(); in checkRAWHazards()
646 const MCSchedModel &SM = STI.getSchedModel(); in addRegisterRead()

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