| /freebsd/contrib/bearssl/src/ec/ |
| H A D | ec_prime_i15.c | 153 #define MADD(d, a) (0x1000 + ((d) << 8) + ((a) << 4)) macro
225 MADD(t1, Px),
232 MADD(t1, t3),
233 MADD(t1, t3),
239 MADD(t3, t3),
241 MADD(t2, t2),
255 MADD(Pz, t4),
406 MADD(t1, P2y),
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| H A D | ec_prime_i31.c | 152 #define MADD(d, a) (0x1000 + ((d) << 8) + ((a) << 4)) macro
224 MADD(t1, Px),
231 MADD(t1, t3),
232 MADD(t1, t3),
238 MADD(t3, t3),
240 MADD(t2, t2),
254 MADD(Pz, t4),
405 MADD(t1, P2y),
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedPredNeoverse.td | 49 // Identify "[SU]?(MADD|MSUB)L?" as the alias for "[SU]?(MUL|MNEG)L?".
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| H A D | AArch64SchedOryon.td | 817 (instregex "^MADD(W|X)rrr", "^MSUB(W|X)rrr",
1395 def : InstRW<[ORYONWrite_4Cyc_FP0123], (instregex "^(F|FN)MADD", "^(F|FN)MSUB")>;
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| H A D | AArch64SchedCyclone.td | 193 // MUL/MNEG are aliases for MADD/MSUB.
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| H A D | AArch64InstrFormats.td | 2618 // MADD/MSUB generation is decided by MachineCombiner.cpp
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| H A D | AArch64InstrInfo.td | 2402 defm MADD : MulAccum<0, "madd">;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 3186 case CASE_VMA_OPCODE_LMULS(MADD, VX): in findCommutedOpIndices()
3210 case CASE_VMA_OPCODE_LMULS(MADD, VV): in findCommutedOpIndices()
3384 case CASE_VMA_OPCODE_LMULS(MADD, VX): in commuteInstructionImpl()
3410 CASE_VMA_CHANGE_OPCODE_LMULS(MACC, MADD, VX) in commuteInstructionImpl()
3411 CASE_VMA_CHANGE_OPCODE_LMULS(MADD, MACC, VX) in commuteInstructionImpl()
3414 CASE_VMA_CHANGE_OPCODE_LMULS(MACC, MADD, VV) in commuteInstructionImpl()
3427 case CASE_VMA_OPCODE_LMULS(MADD, VV): in commuteInstructionImpl()
3441 CASE_VMA_CHANGE_OPCODE_LMULS(MADD, MACC, VV) in commuteInstructionImpl()
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| H A D | RISCVInstrFormats.td | 147 def OPC_MADD : RISCVOpcode<"MADD", 0b1000011>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | P9InstrResources.td | 405 (instregex "MADD(HD|HDU|LD|LD8)$"),
479 (instregex "F(N)?MADD(S)?_rec$"),
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsScheduleP5600.td | 201 def : InstRW<[P5600WriteAL2MAdd], (instrs MADD, MADDU, MSUB, MSUBU,
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| H A D | MipsInstrInfo.td | 2385 // MADD*/MSUB*
2386 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
2404 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
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| H A D | MicroMipsInstrInfo.td | 1112 def PseudoMADD_MM : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
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| H A D | MipsScheduleGeneric.td | 147 def : InstRW<[GenericWriteHILO], (instrs MADD, MADDU, MSUB, MSUBU)>;
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