| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 162 bool LegalOperations = false; member in __anon666e37100111::DAGCombiner
842 return TLI.isOperationLegalOrCustom(Opcode, VT, LegalOperations); in hasOperation()
1381 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); in SimplifyDemandedBits()
1400 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); in SimplifyDemandedVectorElts()
1500 if (!LegalOperations) in PromoteIntBinOp()
1568 if (!LegalOperations) in PromoteIntShiftOp()
1617 if (!LegalOperations) in PromoteExtend()
1645 if (!LegalOperations) in PromoteLoad()
1730 LegalOperations = Level >= AfterLegalizeVectorOps; in Run()
2569 if ((!LegalOperations || hasOperation(ISD::AVGCEILU, VT)) && in foldSubToAvg()
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| H A D | TargetLowering.cpp | 1070 if (TLO.LegalOperations() && !TLI.isOperationLegal(AVGOpc, VT)) in combineShiftToAVG()
1849 (!TLO.LegalOperations() || isOperationLegal(ISD::SHL, SmallVT))) { in SimplifyDemandedBits()
1873 (!TLO.LegalOperations() || isOperationLegal(ISD::SHL, HalfVT))) { in SimplifyDemandedBits()
1976 (!TLO.LegalOperations() || isOperationLegal(ISD::SRL, HalfVT)) && in SimplifyDemandedBits()
2057 if (!TLO.LegalOperations() || in SimplifyDemandedBits()
2219 if ((!TLO.LegalOperations() || isOperationLegal(ISD::SHL, VT)) && in SimplifyDemandedBits()
2224 if ((!TLO.LegalOperations() || isOperationLegal(ISD::SRL, VT)) && in SimplifyDemandedBits()
2321 if (!TLO.LegalOperations() || isOperationLegal(ShiftOpcode, VT)) { in SimplifyDemandedBits()
2440 if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) in SimplifyDemandedBits()
2496 if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) in SimplifyDemandedBits()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.h | 58 bool LegalOperations) const override { in canCombineTruncStore() argument
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| H A D | AMDGPUISelLowering.h | 200 bool LegalOperations, bool ForCodeSize,
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| H A D | AMDGPUISelLowering.cpp | 909 SDValue Op, SelectionDAG &DAG, bool LegalOperations, bool ForCodeSize, in getNegatedExpression() argument
925 SDValue NegSrc = getNegatedExpression(Src, DAG, LegalOperations, in getNegatedExpression()
935 return TargetLowering::getNegatedExpression(Op, DAG, LegalOperations, in getNegatedExpression()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 1091 bool LegalOperations, bool ForCodeSize,
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| H A D | X86ISelLowering.cpp | 52865 bool LegalOperations = !DCI.isBeforeLegalizeOps(); in combineFneg() local
52867 TLI.getNegatedExpression(Arg, DAG, LegalOperations, CodeSize)) in combineFneg()
52874 bool LegalOperations, in getNegatedExpression() argument
52912 Op.getOperand(i), DAG, LegalOperations, ForCodeSize, Depth + 1); in getNegatedExpression()
52930 getNegatedExpression(Op.getOperand(0), DAG, LegalOperations, in getNegatedExpression()
52936 return TargetLowering::getNegatedExpression(Op, DAG, LegalOperations, in getNegatedExpression()
54047 bool LegalOperations = !DCI.isBeforeLegalizeOps(); in combineFMA() local
54048 if (SDValue NegV = TLI.getCheaperNegatedExpression(V, DAG, LegalOperations, in combineFMA()
54059 Vec, DAG, LegalOperations, CodeSize)) { in combineFMA()
54108 bool LegalOperations = !DCI.isBeforeLegalizeOps(); in combineFMADDSUB() local
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 3942 bool LegalOperations() const { return LegalOps; } in LegalOperations() function
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