| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 165 bool LegalOperations = false; member in __anon666e37100111::DAGCombiner
855 return TLI.isOperationLegalOrCustom(Opcode, VT, LegalOperations); in hasOperation()
1438 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); in SimplifyDemandedBits()
1457 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); in SimplifyDemandedVectorElts()
1557 if (!LegalOperations) in PromoteIntBinOp()
1625 if (!LegalOperations) in PromoteIntShiftOp()
1674 if (!LegalOperations) in PromoteExtend()
1702 if (!LegalOperations) in PromoteLoad()
1787 LegalOperations = Level >= AfterLegalizeVectorOps; in Run()
2653 if ((!LegalOperations || hasOperation(ISD::AVGCEILU, VT)) && in foldSubToAvg()
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| H A D | TargetLowering.cpp | 1125 if (TLO.LegalOperations() && !TLI.isOperationLegal(AVGOpc, VT)) in combineShiftToAVG()
1891 (!TLO.LegalOperations() || isOperationLegal(ISD::SHL, SmallVT))) { in SimplifyDemandedBits()
1915 (!TLO.LegalOperations() || isOperationLegal(ISD::SHL, HalfVT))) { in SimplifyDemandedBits()
2029 (!TLO.LegalOperations() || isOperationLegal(ISD::SRL, HalfVT)) && in SimplifyDemandedBits()
2125 if (!TLO.LegalOperations() || in SimplifyDemandedBits()
2287 if ((!TLO.LegalOperations() || isOperationLegal(ISD::SHL, VT)) && in SimplifyDemandedBits()
2292 if ((!TLO.LegalOperations() || isOperationLegal(ISD::SRL, VT)) && in SimplifyDemandedBits()
2389 if (!TLO.LegalOperations() || isOperationLegal(ShiftOpcode, VT)) { in SimplifyDemandedBits()
2508 if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) in SimplifyDemandedBits()
2560 if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) in SimplifyDemandedBits()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.h | 58 bool LegalOperations) const override { in canCombineTruncStore() argument
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| H A D | AMDGPUISelLowering.h | 203 bool LegalOperations, bool ForCodeSize,
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| H A D | AMDGPUISelLowering.cpp | 928 SDValue Op, SelectionDAG &DAG, bool LegalOperations, bool ForCodeSize, in getNegatedExpression() argument
944 SDValue NegSrc = getNegatedExpression(Src, DAG, LegalOperations, in getNegatedExpression()
954 return TargetLowering::getNegatedExpression(Op, DAG, LegalOperations, in getNegatedExpression()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 1177 bool LegalOperations, bool ForCodeSize,
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| H A D | X86ISelLowering.cpp | 54689 bool LegalOperations = !DCI.isBeforeLegalizeOps(); in combineFneg() local
54691 TLI.getNegatedExpression(Arg, DAG, LegalOperations, CodeSize)) in combineFneg()
54698 bool LegalOperations, in getNegatedExpression() argument
54740 Op.getOperand(i), DAG, LegalOperations, ForCodeSize, Depth + 1); in getNegatedExpression()
54761 getNegatedExpression(Op.getOperand(0), DAG, LegalOperations, in getNegatedExpression()
54767 return TargetLowering::getNegatedExpression(Op, DAG, LegalOperations, in getNegatedExpression()
55916 bool LegalOperations = !DCI.isBeforeLegalizeOps(); in combineFMA() local
55917 if (SDValue NegV = TLI.getCheaperNegatedExpression(V, DAG, LegalOperations, in combineFMA()
55928 Vec, DAG, LegalOperations, CodeSize)) { in combineFMA()
55982 bool LegalOperations = !DCI.isBeforeLegalizeOps(); in combineFMADDSUB() local
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 4097 bool LegalOperations() const { return LegalOps; } in LegalOperations() function
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