Lines Matching refs:LegalOperations
1070 if (TLO.LegalOperations() && !TLI.isOperationLegal(AVGOpc, VT)) in combineShiftToAVG()
1849 (!TLO.LegalOperations() || isOperationLegal(ISD::SHL, SmallVT))) { in SimplifyDemandedBits()
1873 (!TLO.LegalOperations() || isOperationLegal(ISD::SHL, HalfVT))) { in SimplifyDemandedBits()
1976 (!TLO.LegalOperations() || isOperationLegal(ISD::SRL, HalfVT)) && in SimplifyDemandedBits()
2057 if (!TLO.LegalOperations() || in SimplifyDemandedBits()
2219 if ((!TLO.LegalOperations() || isOperationLegal(ISD::SHL, VT)) && in SimplifyDemandedBits()
2224 if ((!TLO.LegalOperations() || isOperationLegal(ISD::SRL, VT)) && in SimplifyDemandedBits()
2321 if (!TLO.LegalOperations() || isOperationLegal(ShiftOpcode, VT)) { in SimplifyDemandedBits()
2440 if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) in SimplifyDemandedBits()
2496 if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) in SimplifyDemandedBits()
2513 if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) { in SimplifyDemandedBits()
2688 if (!TLO.LegalOperations() && !VT.isVector() && !SrcVT.isVector() && in SimplifyDemandedBits()