| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegacyLegalizerInfo.cpp | 30 case Legal: in operator <<()
71 setScalarAction(TargetOpcode::G_ANYEXT, 1, {{1, Legal}}); in LegacyLegalizerInfo()
72 setScalarAction(TargetOpcode::G_ZEXT, 1, {{1, Legal}}); in LegacyLegalizerInfo()
73 setScalarAction(TargetOpcode::G_SEXT, 1, {{1, Legal}}); in LegacyLegalizerInfo()
74 setScalarAction(TargetOpcode::G_TRUNC, 0, {{1, Legal}}); in LegacyLegalizerInfo()
75 setScalarAction(TargetOpcode::G_TRUNC, 1, {{1, Legal}}); in LegacyLegalizerInfo()
77 setScalarAction(TargetOpcode::G_INTRINSIC, 0, {{1, Legal}}); in LegacyLegalizerInfo()
78 setScalarAction(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, 0, {{1, Legal}}); in LegacyLegalizerInfo()
79 setScalarAction(TargetOpcode::G_INTRINSIC_CONVERGENT, 0, {{1, Legal}}); in LegacyLegalizerInfo()
81 {{1, Legal}}); in LegacyLegalizerInfo()
[all …]
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| H A D | LegalizerInfo.cpp | 45 case Legal: in operator <<()
104 case Legal: in hasNoSimpleLoops()
123 if (Rule.getAction() == Custom || Rule.getAction() == Legal) in mutationIsSane()
386 return getAction(MI, MRI).Action == Legal; in isLegal()
394 return Action == Legal || Action == Custom; in isLegalOrCustom()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 119 setOperationAction(ISD::ADD, MVT::i32, Legal); in ARCTargetLowering()
120 setOperationAction(ISD::SUB, MVT::i32, Legal); in ARCTargetLowering()
121 setOperationAction(ISD::AND, MVT::i32, Legal); in ARCTargetLowering()
122 setOperationAction(ISD::SMAX, MVT::i32, Legal); in ARCTargetLowering()
123 setOperationAction(ISD::SMIN, MVT::i32, Legal); in ARCTargetLowering()
125 setOperationAction(ISD::ADDC, MVT::i32, Legal); in ARCTargetLowering()
126 setOperationAction(ISD::ADDE, MVT::i32, Legal); in ARCTargetLowering()
127 setOperationAction(ISD::SUBC, MVT::i32, Legal); in ARCTargetLowering()
128 setOperationAction(ISD::SUBE, MVT::i32, Legal); in ARCTargetLowering()
131 setOperationAction(ISD::SHL, MVT::i32, Legal); in ARCTargetLowering()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 133 setOperationAction(ISD::ADD, VecTy, Legal); in MipsSETargetLowering()
134 setOperationAction(ISD::SUB, VecTy, Legal); in MipsSETargetLowering()
135 setOperationAction(ISD::LOAD, VecTy, Legal); in MipsSETargetLowering()
136 setOperationAction(ISD::STORE, VecTy, Legal); in MipsSETargetLowering()
137 setOperationAction(ISD::BITCAST, VecTy, Legal); in MipsSETargetLowering()
144 setOperationAction(ISD::ADDC, MVT::i32, Legal); in MipsSETargetLowering()
145 setOperationAction(ISD::ADDE, MVT::i32, Legal); in MipsSETargetLowering()
150 setOperationAction(ISD::MUL, MVT::v2i16, Legal); in MipsSETargetLowering()
220 setOperationAction(ISD::MUL, MVT::i64, Legal); in MipsSETargetLowering()
240 setOperationAction(ISD::LOAD, MVT::i32, Legal); in MipsSETargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | LoopVectorize.cpp | 910 LoopVectorizationLegality *Legal, in LoopVectorizationCostModel() argument
918 : ScalarEpilogueStatus(SEL), TheLoop(L), PSE(PSE), LI(LI), Legal(Legal), in LoopVectorizationCostModel()
1177 if (Op != Legal->getPrimaryInduction() && TTI.isTruncateFree(SrcTy, DestTy)) in isOptimizableIVTruncate()
1181 return Legal->isInductionPhi(Op); in isOptimizableIVTruncate()
1210 return Legal->isConsecutivePtr(DataType, Ptr) && in isLegalMaskedStore()
1218 return Legal->isConsecutivePtr(DataType, Ptr) && in isLegalMaskedLoad()
1240 return (all_of(Legal->getReductionVars(), [&](auto &Reduction) -> bool { in canVectorizeReductions()
1311 !(EnableEarlyExitVectorization && Legal->hasUncountableEarlyExit())) { in requiresScalarEpilogue()
1345 if (!Legal->canFoldTailByMasking()) { in setTailFoldingStyles()
1399 return foldTailByMasking() || Legal->blockNeedsPredication(BB); in blockNeedsPredicationForAnyReason()
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| H A D | VPRecipeBuilder.h | 61 LoopVectorizationLegality *Legal; variable
149 LoopVectorizationLegality *Legal, in VPRecipeBuilder() argument
154 : Plan(Plan), OrigLoop(OrigLoop), TLI(TLI), TTI(TTI), Legal(Legal), in VPRecipeBuilder()
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| H A D | LoopVectorizationPlanner.h | 425 LoopVectorizationLegality *Legal; variable
466 const TargetTransformInfo &TTI, LoopVectorizationLegality *Legal, in LoopVectorizationPlanner() argument
470 : OrigLoop(L), LI(LI), DT(DT), TLI(TLI), TTI(TTI), Legal(Legal), CM(CM), in LoopVectorizationPlanner()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegalizerInfo.h | 48 Legal, enumerator
157 case LegacyLegalizeActions::Legal: in LegalizeActionStep()
158 Action = LegalizeActions::Legal; in LegalizeActionStep()
619 return actionIf(LegalizeAction::Legal, Predicate); in legalIf()
623 return actionFor(LegalizeAction::Legal, Types); in legalFor()
628 return actionFor(LegalizeAction::Legal, Types); in legalFor()
633 return actionFor(LegalizeAction::Legal, Types); in legalFor()
639 return actionFor(LegalizeAction::Legal, Types); in legalFor()
645 return actionFor(LegalizeAction::Legal, Types); in legalFor()
651 return actionForTypeWithAnyImm(LegalizeAction::Legal, Types); in legalForTypeWithAnyImm()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 216 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); in PPCTargetLowering()
217 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal); in PPCTargetLowering()
236 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f16, Legal); in PPCTargetLowering()
237 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Legal); in PPCTargetLowering()
238 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Legal); in PPCTargetLowering()
239 setTruncStoreAction(MVT::f64, MVT::f16, Legal); in PPCTargetLowering()
240 setTruncStoreAction(MVT::f32, MVT::f16, Legal); in PPCTargetLowering()
258 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
259 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
260 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 187 setOperationAction(ISD::ABS, VT, Legal); in SystemZTargetLowering()
289 setOperationAction(ISD::ABS, MVT::i128, Legal); in SystemZTargetLowering()
328 {MVT::i8, MVT::i16, MVT::i32}, Legal); in SystemZTargetLowering()
330 {MVT::i8, MVT::i16}, Legal); in SystemZTargetLowering()
332 MVT::i8, Legal); in SystemZTargetLowering()
343 setOperationAction(ISD::TRAP, MVT::Other, Legal); in SystemZTargetLowering()
348 setOperationAction(ISD::CTLZ, MVT::i64, Legal); in SystemZTargetLowering()
354 setOperationAction(ISD::CTTZ, MVT::i64, Legal); in SystemZTargetLowering()
360 setOperationAction(ISD::CTPOP, MVT::i64, Legal); in SystemZTargetLowering()
414 if (getOperationAction(Opcode, VT) == Legal) in SystemZTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/ |
| H A D | IRSimilarityIdentifier.h | 77 enum InstrType { Legal, Illegal, Invisible }; enumerator
126 bool Legal = false; member
531 return Legal; in visitBranchInst()
536 return Legal; in visitPHINode()
557 return EnableIntrinsics ? Legal : Illegal; in visitIntrinsicInst()
580 return Legal; in visitCallInst()
588 InstrType visitInstruction(Instruction &I) { return Legal; } in visitInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1578 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); in HexagonTargetLowering()
1579 setOperationAction(ISD::ConstantFP, MVT::f64, Legal); in HexagonTargetLowering()
1580 setOperationAction(ISD::TRAP, MVT::Other, Legal); in HexagonTargetLowering()
1581 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal); in HexagonTargetLowering()
1629 setOperationAction(LegalIntOp, MVT::i32, Legal); in HexagonTargetLowering()
1630 setOperationAction(LegalIntOp, MVT::i64, Legal); in HexagonTargetLowering()
1655 setOperationAction(ISD::CTPOP, MVT::i64, Legal); in HexagonTargetLowering()
1657 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); in HexagonTargetLowering()
1658 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal); in HexagonTargetLowering()
1659 setOperationAction(ISD::BSWAP, MVT::i32, Legal); in HexagonTargetLowering()
[all …]
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| H A D | HexagonISelLoweringHVX.cpp | 116 setOperationAction(ISD::VECTOR_SHUFFLE, ByteV, Legal); in initializeHVXLowering()
117 setOperationAction(ISD::VECTOR_SHUFFLE, ByteW, Legal); in initializeHVXLowering()
129 setOperationAction(ISD::FADD, T, Legal); in initializeHVXLowering()
130 setOperationAction(ISD::FSUB, T, Legal); in initializeHVXLowering()
131 setOperationAction(ISD::FMUL, T, Legal); in initializeHVXLowering()
132 setOperationAction(ISD::FMINIMUMNUM, T, Legal); in initializeHVXLowering()
133 setOperationAction(ISD::FMAXIMUMNUM, T, Legal); in initializeHVXLowering()
138 setOperationAction(ISD::SPLAT_VECTOR, T, Legal); in initializeHVXLowering()
139 setOperationAction(ISD::SPLAT_VECTOR, T, Legal); in initializeHVXLowering()
187 setOperationAction(ISD::FP_ROUND, MVT::v64f16, Legal); in initializeHVXLowering()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 601 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal); in NVPTXTargetLowering()
603 setOperationAction(ISD::READSTEADYCOUNTER, MVT::i64, Legal); in NVPTXTargetLowering()
605 setFP16OperationAction(ISD::SETCC, MVT::f16, Legal, Promote); in NVPTXTargetLowering()
606 setFP16OperationAction(ISD::SETCC, MVT::v2f16, Legal, Expand); in NVPTXTargetLowering()
614 setBF16OperationAction(ISD::SETCC, MVT::v2bf16, Legal, Expand); in NVPTXTargetLowering()
615 setBF16OperationAction(ISD::SETCC, MVT::bf16, Legal, Promote); in NVPTXTargetLowering()
671 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal); in NVPTXTargetLowering()
672 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); in NVPTXTargetLowering()
673 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal); in NVPTXTargetLowering()
674 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); in NVPTXTargetLowering()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaISelLowering.cpp | 85 Subtarget.hasSEXT() ? Legal : Expand); in XtensaTargetLowering()
112 setOperationAction(ISD::BR_CC, MVT::i32, Legal); in XtensaTargetLowering()
120 setOperationAction(ISD::BR_CC, MVT::f32, Legal); in XtensaTargetLowering()
136 setOperationAction(ISD::MUL, MVT::i32, Legal); in XtensaTargetLowering()
141 setOperationAction(ISD::MULHU, MVT::i32, Legal); in XtensaTargetLowering()
142 setOperationAction(ISD::MULHS, MVT::i32, Legal); in XtensaTargetLowering()
152 setOperationAction(ISD::SDIV, MVT::i32, Legal); in XtensaTargetLowering()
153 setOperationAction(ISD::UDIV, MVT::i32, Legal); in XtensaTargetLowering()
154 setOperationAction(ISD::SREM, MVT::i32, Legal); in XtensaTargetLowering()
155 setOperationAction(ISD::UREM, MVT::i32, Legal); in XtensaTargetLowering()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VETargetTransformInfo.h | 118 return VPLegalization(VPLegalization::Legal, VPLegalization::Legal); in getVPLegalizationStrategy()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1619 setOperationAction(ISD::LOAD, MVT::v2i32, Legal); in SparcTargetLowering()
1620 setOperationAction(ISD::STORE, MVT::v2i32, Legal); in SparcTargetLowering()
1621 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Legal); in SparcTargetLowering()
1622 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Legal); in SparcTargetLowering()
1698 Subtarget->isVIS3() ? Legal : Expand); in SparcTargetLowering()
1700 Subtarget->isVIS3() ? Legal : Expand); in SparcTargetLowering()
1727 setOperationAction(ISD::ADDC, MVT::i32, Legal); in SparcTargetLowering()
1728 setOperationAction(ISD::ADDE, MVT::i32, Legal); in SparcTargetLowering()
1729 setOperationAction(ISD::SUBC, MVT::i32, Legal); in SparcTargetLowering()
1730 setOperationAction(ISD::SUBE, MVT::i32, Legal); in SparcTargetLowering()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 97 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal); in LoongArchTargetLowering()
98 setOperationAction(ISD::TRAP, MVT::Other, Legal); in LoongArchTargetLowering()
111 setOperationAction(ISD::BITREVERSE, GRLenVT, Legal); in LoongArchTargetLowering()
193 setOperationAction(ISD::FMA, MVT::f32, Legal); in LoongArchTargetLowering()
194 setOperationAction(ISD::FMINNUM_IEEE, MVT::f32, Legal); in LoongArchTargetLowering()
195 setOperationAction(ISD::FMINNUM, MVT::f32, Legal); in LoongArchTargetLowering()
196 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f32, Legal); in LoongArchTargetLowering()
197 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in LoongArchTargetLowering()
198 setOperationAction(ISD::FCANONICALIZE, MVT::f32, Legal); in LoongArchTargetLowering()
199 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Legal); in LoongArchTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | IRSimilarityIdentifier.cpp | 51 : Inst(&I), Legal(Legality), IDL(&IDList) { in IRInstructionData()
223 if (!A.Legal || !B.Legal) in isClose()
299 case InstrType::Legal: in convertToUnsignedVec()
503 if (!A.Legal || !B.Legal) in isSimilar()
812 if (!ItA->Legal || !ItB->Legal) in compareStructure()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 202 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal); in addTypeForNEON()
203 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); in addTypeForNEON()
227 setOperationAction(Opcode, VT, Legal); in addTypeForNEON()
230 setOperationAction(Opcode, VT, Legal); in addTypeForNEON()
250 setOperationAction(ISD::BITCAST, VT, Legal); in setAllExpand()
251 setOperationAction(ISD::LOAD, VT, Legal); in setAllExpand()
252 setOperationAction(ISD::STORE, VT, Legal); in setAllExpand()
253 setOperationAction(ISD::UNDEF, VT, Legal); in setAllExpand()
275 setOperationAction(ISD::SMIN, VT, Legal); in addMVEVectorTypes()
276 setOperationAction(ISD::SMAX, VT, Legal); in addMVEVectorTypes()
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| /freebsd/contrib/netbsd-tests/lib/libc/db/ |
| H A D | README | 14 Legal command characters are as follows:
39 Legal key/data characters are as follows:
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 203 Legal, // The target natively supports this operation. enumerator
1278 return Legal; in getCustomOperationAction()
1309 if (Action != Legal) in getFixedPointOperationAction()
1359 (getOperationAction(Op, VT) == Legal ||
1373 (getOperationAction(Op, VT) == Legal ||
1387 (getOperationAction(Op, VT) == Legal ||
1463 getOperationAction(Op, VT) == Legal; in isOperationLegal()
1482 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal; in isLoadExtLegal()
1488 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal || in isLoadExtLegalOrCustom()
1503 assert((Action == Legal || Action == Expand) && in getAtomicLoadExtAction()
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| /freebsd/crypto/krb5/src/plugins/kdb/db2/libdb2/test/ |
| H A D | README | 22 Legal command characters are as follows:
47 Legal key/data characters are as follows:
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| /freebsd/lib/libc/db/test/ |
| H A D | README | 21 Legal command characters are as follows:
46 Legal key/data characters are as follows:
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| /freebsd/sys/contrib/openzfs/module/icp/asm-x86_64/modes/ |
| H A D | THIRDPARTYLICENSE.openssl | 16 "Legal Entity" shall mean the union of the acting entity and all
24 "You" (or "Your") shall mean an individual or Legal Entity
53 or by an individual or Legal Entity authorized to submit on behalf of
63 "Contributor" shall mean Licensor and any individual or Legal Entity
|