| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegacyLegalizerInfo.cpp | 30 case Legal: in operator <<()
31 OS << "Legal"; in operator <<()
71 setScalarAction(TargetOpcode::G_ANYEXT, 1, {{1, Legal}}); in LegacyLegalizerInfo()
72 setScalarAction(TargetOpcode::G_ZEXT, 1, {{1, Legal}}); in LegacyLegalizerInfo()
73 setScalarAction(TargetOpcode::G_SEXT, 1, {{1, Legal}}); in LegacyLegalizerInfo()
74 setScalarAction(TargetOpcode::G_TRUNC, 0, {{1, Legal}}); in LegacyLegalizerInfo()
75 setScalarAction(TargetOpcode::G_TRUNC, 1, {{1, Legal}}); in LegacyLegalizerInfo()
77 setScalarAction(TargetOpcode::G_INTRINSIC, 0, {{1, Legal}}); in LegacyLegalizerInfo()
78 setScalarAction(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, 0, {{1, Legal}}); in LegacyLegalizerInfo()
79 setScalarAction(TargetOpcode::G_INTRINSIC_CONVERGENT, 0, {{1, Legal}}); in LegacyLegalizerInfo()
[all...] |
| H A D | LegalizerInfo.cpp | 39 case Legal: in operator <<()
98 case Legal: in hasNoSimpleLoops()
117 if (Rule.getAction() == Custom || Rule.getAction() == Legal) in mutationIsSane()
364 return getAction(MI, MRI).Action == Legal; in isLegal()
372 return Action == Legal || Action == Custom; in isLegalOrCustom()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 118 setOperationAction(ISD::ADD, MVT::i32, Legal); in ARCTargetLowering()
119 setOperationAction(ISD::SUB, MVT::i32, Legal); in ARCTargetLowering()
120 setOperationAction(ISD::AND, MVT::i32, Legal); in ARCTargetLowering()
121 setOperationAction(ISD::SMAX, MVT::i32, Legal); in ARCTargetLowering()
122 setOperationAction(ISD::SMIN, MVT::i32, Legal); in ARCTargetLowering()
124 setOperationAction(ISD::ADDC, MVT::i32, Legal); in ARCTargetLowering()
125 setOperationAction(ISD::ADDE, MVT::i32, Legal); in ARCTargetLowering()
126 setOperationAction(ISD::SUBC, MVT::i32, Legal); in ARCTargetLowering()
127 setOperationAction(ISD::SUBE, MVT::i32, Legal); in ARCTargetLowering()
130 setOperationAction(ISD::SHL, MVT::i32, Legal); in ARCTargetLowering()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 94 setOperationAction(ISD::ADD, VecTy, Legal); in MipsSETargetLowering()
95 setOperationAction(ISD::SUB, VecTy, Legal); in MipsSETargetLowering()
96 setOperationAction(ISD::LOAD, VecTy, Legal); in MipsSETargetLowering()
97 setOperationAction(ISD::STORE, VecTy, Legal); in MipsSETargetLowering()
98 setOperationAction(ISD::BITCAST, VecTy, Legal); in MipsSETargetLowering()
105 setOperationAction(ISD::ADDC, MVT::i32, Legal); in MipsSETargetLowering()
106 setOperationAction(ISD::ADDE, MVT::i32, Legal); in MipsSETargetLowering()
111 setOperationAction(ISD::MUL, MVT::v2i16, Legal); in MipsSETargetLowering()
181 setOperationAction(ISD::MUL, MVT::i64, Legal); in MipsSETargetLowering()
201 setOperationAction(ISD::LOAD, MVT::i32, Legal); in MipsSETargetLowering()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VPRecipeBuilder.h | 36 LoopVectorizationLegality *Legal; variable
107 LoopVectorizationLegality *Legal, in VPRecipeBuilder() argument
110 : Plan(Plan), OrigLoop(OrigLoop), TLI(TLI), Legal(Legal), CM(CM), in VPRecipeBuilder()
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| H A D | LoopVectorize.cpp | 482 Builder(PSE.getSE()->getContext()), Legal(LVL), Cost(CM), BFI(BFI), in InnerLoopVectorizer()
681 LoopVectorizationLegality *Legal; member in llvm::InnerLoopVectorizer
1018 LoopVectorizationLegality *Legal, in LoopVectorizationCostModel() argument
1025 : ScalarEpilogueStatus(SEL), TheLoop(L), PSE(PSE), LI(LI), Legal(Legal), in LoopVectorizationCostModel()
1277 if (Op != Legal->getPrimaryInduction() && TTI.isTruncateFree(SrcTy, DestTy)) in isOptimizableIVTruncate()
1281 return Legal->isInductionPhi(Op); in isOptimizableIVTruncate()
1307 return Legal->isConsecutivePtr(DataType, Ptr) && in isLegalMaskedStore()
1314 return Legal->isConsecutivePtr(DataType, Ptr) && in isLegalMaskedLoad()
1336 return (all_of(Legal->getReductionVars(), [&](auto &Reduction) -> bool { in canVectorizeReductions()
1455 if (!Legal->canFoldTailByMasking()) { in setTailFoldingStyles()
[all …]
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| H A D | LoopVectorizationPlanner.h | 315 LoopVectorizationLegality *Legal; variable
350 const TargetTransformInfo &TTI, LoopVectorizationLegality *Legal, in LoopVectorizationPlanner() argument
354 : OrigLoop(L), LI(LI), DT(DT), TLI(TLI), TTI(TTI), Legal(Legal), CM(CM), in LoopVectorizationPlanner()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 197 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); in PPCTargetLowering()
198 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal); in PPCTargetLowering()
214 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Legal); in PPCTargetLowering()
215 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Legal); in PPCTargetLowering()
216 setTruncStoreAction(MVT::f64, MVT::f16, Legal); in PPCTargetLowering()
217 setTruncStoreAction(MVT::f32, MVT::f16, Legal); in PPCTargetLowering()
233 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
234 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
235 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
236 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); in PPCTargetLowering()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 178 setOperationAction(ISD::ABS, VT, Legal); in SystemZTargetLowering()
229 setOperationAction(ISD::STRICT_FP_TO_SINT, VT, Legal); in SystemZTargetLowering()
231 setOperationAction(ISD::STRICT_FP_TO_UINT, VT, Legal); in SystemZTargetLowering()
234 setOperationAction(ISD::STRICT_SINT_TO_FP, VT, Legal); in SystemZTargetLowering()
236 setOperationAction(ISD::STRICT_UINT_TO_FP, VT, Legal); in SystemZTargetLowering()
304 {MVT::i8, MVT::i16, MVT::i32}, Legal); in SystemZTargetLowering()
306 {MVT::i8, MVT::i16}, Legal); in SystemZTargetLowering()
308 MVT::i8, Legal); in SystemZTargetLowering()
319 setOperationAction(ISD::TRAP, MVT::Other, Legal); in SystemZTargetLowering()
333 setOperationAction(ISD::CTLZ, MVT::i64, Legal); in SystemZTargetLowering()
[all …]
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegalizerInfo.h | 47 Legal, enumerator
158 case LegacyLegalizeActions::Legal: in LegalizeActionStep()
159 Action = LegalizeActions::Legal; in LegalizeActionStep()
596 return actionIf(LegalizeAction::Legal, Predicate); in legalIf()
600 return actionFor(LegalizeAction::Legal, Types); in legalFor()
605 return actionFor(LegalizeAction::Legal, Types); in legalFor()
611 return actionForTypeWithAnyImm(LegalizeAction::Legal, Types); in legalForTypeWithAnyImm()
617 return actionForTypeWithAnyImm(LegalizeAction::Legal, Types); in legalForTypeWithAnyImm()
625 return actionIf(LegalizeAction::Legal, in legalForTypesWithMemDesc()
632 return actionForCartesianProduct(LegalizeAction::Legal, Types); in legalForCartesianProduct()
[all …]
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/ |
| H A D | IRSimilarityIdentifier.h | 69 /// Legal Instructions are considered when looking at similarity between
77 enum InstrType { Legal, Illegal, Invisible }; enumerator
126 bool Legal = false; member
528 return Legal; in visitBranchInst()
533 return Legal; in visitPHINode()
558 return EnableIntrinsics ? Legal : Illegal; in visitIntrinsicInst()
581 return Legal; in visitCallInst()
589 InstrType visitInstruction(Instruction &I) { return Legal; } in visitInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1511 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); in HexagonTargetLowering()
1512 setOperationAction(ISD::ConstantFP, MVT::f64, Legal); in HexagonTargetLowering()
1513 setOperationAction(ISD::TRAP, MVT::Other, Legal); in HexagonTargetLowering()
1561 setOperationAction(LegalIntOp, MVT::i32, Legal); in HexagonTargetLowering()
1562 setOperationAction(LegalIntOp, MVT::i64, Legal); in HexagonTargetLowering()
1587 setOperationAction(ISD::CTPOP, MVT::i64, Legal); in HexagonTargetLowering()
1589 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); in HexagonTargetLowering()
1590 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal); in HexagonTargetLowering()
1591 setOperationAction(ISD::BSWAP, MVT::i32, Legal); in HexagonTargetLowering()
1592 setOperationAction(ISD::BSWAP, MVT::i64, Legal); in HexagonTargetLowering()
[all...] |
| H A D | HexagonISelLoweringHVX.cpp | 116 setOperationAction(ISD::VECTOR_SHUFFLE, ByteV, Legal); in initializeHVXLowering()
117 setOperationAction(ISD::VECTOR_SHUFFLE, ByteW, Legal); in initializeHVXLowering()
127 setOperationAction(ISD::FADD, T, Legal); in initializeHVXLowering()
128 setOperationAction(ISD::FSUB, T, Legal); in initializeHVXLowering()
129 setOperationAction(ISD::FMUL, T, Legal); in initializeHVXLowering()
130 setOperationAction(ISD::FMINNUM, T, Legal); in initializeHVXLowering()
131 setOperationAction(ISD::FMAXNUM, T, Legal); in initializeHVXLowering()
136 setOperationAction(ISD::SPLAT_VECTOR, T, Legal); in initializeHVXLowering()
137 setOperationAction(ISD::SPLAT_VECTOR, T, Legal); in initializeHVXLowering()
185 setOperationAction(ISD::FP_ROUND, MVT::v64f16, Legal); in initializeHVXLowering()
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 498 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal); in NVPTXTargetLowering()
500 setOperationAction(ISD::READSTEADYCOUNTER, MVT::i64, Legal); in NVPTXTargetLowering()
502 setFP16OperationAction(ISD::SETCC, MVT::f16, Legal, Promote); in NVPTXTargetLowering()
503 setFP16OperationAction(ISD::SETCC, MVT::v2f16, Legal, Expand); in NVPTXTargetLowering()
511 setBF16OperationAction(ISD::SETCC, MVT::v2bf16, Legal, Expand); in NVPTXTargetLowering()
512 setBF16OperationAction(ISD::SETCC, MVT::bf16, Legal, Promote); in NVPTXTargetLowering()
556 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal); in NVPTXTargetLowering()
557 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); in NVPTXTargetLowering()
558 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal); in NVPTXTargetLowering()
559 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); in NVPTXTargetLowering()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VETargetTransformInfo.h | 117 return VPLegalization(VPLegalization::Legal, VPLegalization::Legal); in getVPLegalizationStrategy()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 95 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal); in LoongArchTargetLowering()
96 setOperationAction(ISD::TRAP, MVT::Other, Legal); in LoongArchTargetLowering()
105 setOperationAction(ISD::BITREVERSE, GRLenVT, Legal); in LoongArchTargetLowering()
172 setOperationAction(ISD::FMA, MVT::f32, Legal); in LoongArchTargetLowering()
173 setOperationAction(ISD::FMINNUM_IEEE, MVT::f32, Legal); in LoongArchTargetLowering()
174 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f32, Legal); in LoongArchTargetLowering()
175 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Legal); in LoongArchTargetLowering()
176 setOperationAction(ISD::STRICT_FSETCC, MVT::f32, Legal); in LoongArchTargetLowering()
177 setOperationAction(ISD::IS_FPCLASS, MVT::f32, Legal); in LoongArchTargetLowering()
187 setOperationAction(ISD::FRINT, MVT::f32, Legal); in LoongArchTargetLowering()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | IRSimilarityIdentifier.cpp | 51 : Inst(&I), Legal(Legality), IDL(&IDList) { in IRInstructionData()
224 if (!A.Legal || !B.Legal) in isClose()
300 case InstrType::Legal: in convertToUnsignedVec()
508 if (!A.Legal || !B.Legal) in isSimilar()
818 if (!ItA->Legal || !ItB->Legal) in compareStructure()
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| /freebsd/contrib/netbsd-tests/lib/libc/db/ |
| H A D | README | 14 Legal command characters are as follows:
39 Legal key/data characters are as follows:
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 200 Legal, // The target natively supports this operation. enumerator
1248 return Legal; in getCustomOperationAction()
1279 if (Action != Legal) in getFixedPointOperationAction()
1329 (getOperationAction(Op, VT) == Legal ||
1343 (getOperationAction(Op, VT) == Legal ||
1357 (getOperationAction(Op, VT) == Legal ||
1433 getOperationAction(Op, VT) == Legal; in isOperationLegal()
1452 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal; in isLoadExtLegal()
1458 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal || in isLoadExtLegalOrCustom()
1473 assert((Action == Legal || Action == Expand) && in getAtomicLoadExtAction()
[all …]
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| /freebsd/lib/libc/db/test/ |
| H A D | README | 21 Legal command characters are as follows:
46 Legal key/data characters are as follows:
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | ExpandVectorPredication.cpp | 41 VPINTERNAL_CASE(Legal) \
847 case VPLegalization::Legal: in expandVectorPredication()
857 Job.Strategy.EVLParamStrategy = VPLegalization::Legal; in expandVectorPredication()
861 case VPLegalization::Legal: in expandVectorPredication()
870 Job.Strategy.OpStrategy = VPLegalization::Legal; in expandVectorPredication()
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| /freebsd/sys/contrib/openzfs/module/icp/asm-x86_64/modes/ |
| H A D | THIRDPARTYLICENSE.openssl | 16 "Legal Entity" shall mean the union of the acting entity and all
24 "You" (or "Your") shall mean an individual or Legal Entity
53 or by an individual or Legal Entity authorized to submit on behalf of
63 "Contributor" shall mean Licensor and any individual or Legal Entity
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| /freebsd/crypto/openssl/ |
| H A D | LICENSE.txt | 16 "Legal Entity" shall mean the union of the acting entity and all
24 "You" (or "Your") shall mean an individual or Legal Entity
53 or by an individual or Legal Entity authorized to submit on behalf of
63 "Contributor" shall mean Licensor and any individual or Legal Entity
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 125 setOperationAction(ISD::ConstantFP, T, Legal); in WebAssemblyTargetLowering()
138 setOperationAction(Op, T, Legal); in WebAssemblyTargetLowering()
140 setOperationAction(ISD::FMINIMUM, T, Legal); in WebAssemblyTargetLowering()
141 setOperationAction(ISD::FMAXIMUM, T, Legal); in WebAssemblyTargetLowering()
150 setOperationAction(ISD::FMINIMUM, MVT::v8f16, Legal); in WebAssemblyTargetLowering()
151 setOperationAction(ISD::FMAXIMUM, MVT::v8f16, Legal); in WebAssemblyTargetLowering()
200 setOperationAction(Op, T, Legal); in WebAssemblyTargetLowering()
204 setOperationAction(ISD::ABS, T, Legal); in WebAssemblyTargetLowering()
219 setOperationAction(ISD::SPLAT_VECTOR, T, Legal); in WebAssemblyTargetLowering()
249 setOperationAction(Op, T, Legal); in WebAssemblyTargetLowering()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1628 setOperationAction(ISD::LOAD, MVT::v2i32, Legal); in SparcTargetLowering()
1629 setOperationAction(ISD::STORE, MVT::v2i32, Legal); in SparcTargetLowering()
1630 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Legal); in SparcTargetLowering()
1631 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Legal); in SparcTargetLowering()
1752 Subtarget->usePopc() ? Legal : Expand); in SparcTargetLowering()
1779 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Legal); in SparcTargetLowering()
1781 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Legal); in SparcTargetLowering()
1788 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Legal); in SparcTargetLowering()
1789 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Legal); in SparcTargetLowering()
1871 setOperationAction(ISD::TRAP , MVT::Other, Legal); in SparcTargetLowering()
[all …]
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