| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VPlanHelpers.h | 141 unsigned Lane;
147 VPLane(unsigned Lane) : Lane(Lane) {} in VPLane() argument
148 VPLane(unsigned Lane, Kind LaneKind) : Lane(Lane), LaneKind(LaneKind) {} in VPLane() argument
175 return Lane; in getKnownLane()
186 bool isFirstLane() const { return Lane == 0 && LaneKind == Kind::First; } in isFirstLane()
192 assert(VF.isScalable() && Lane < VF.getKnownMinValue() && in mapToCacheIndex()
194 return VF.getKnownMinValue() + Lane; in mapToCacheIndex()
196 assert(Lane < VF.getKnownMinValue() && in mapToCacheIndex()
198 return Lane; in mapToCacheIndex()
219 std::optional<VPLane> Lane; member
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| H A D | VPlan.cpp | 81 Builder.getInt32(VF.getKnownMinValue() - Lane)); in getAsRuntimeExpr()
83 return Builder.getInt32(Lane); in getAsRuntimeExpr()
252 Value *VPTransformState::get(const VPValue *Def, const VPLane &Lane) { in get() argument
256 if (hasScalarValue(Def, Lane)) in get()
257 return Data.VPV2Scalars[Def][Lane.mapToCacheIndex(VF)]; in get()
259 if (!Lane.isFirstLane() && vputils::isSingleScalar(Def) && in get()
266 if (Lane.getKind() == VPLane::Kind::First && match(Def, m_BuildVector())) { in get()
268 return get(BuildVector->getOperand(Lane.getKnownLane()), true); in get()
274 assert(Lane.isFirstLane() && "cannot get lane > 0 for scalar"); in get()
278 Value *LaneV = Lane.getAsRuntimeExpr(Builder, VF); in get()
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| H A D | VPlanSLP.cpp | 369 for (unsigned Lane = 1, E = MultiNodeOps[0].second.size(); Lane < E; ++Lane) { in reorderMultiNodeOps() local
370 LLVM_DEBUG(dbgs() << " Finding best value for lane " << Lane << "\n"); in reorderMultiNodeOps()
375 dbgs() << *cast<VPInstruction>(Ops.second[Lane])->getUnderlyingInstr() in reorderMultiNodeOps()
377 Candidates.insert(Ops.second[Lane]); in reorderMultiNodeOps()
386 VPValue *Last = FinalOrder[Op].second[Lane - 1]; in reorderMultiNodeOps()
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| H A D | VPlanRecipes.cpp | 527 const VPLane &Lane) { in generatePerLane() argument
532 return Builder.CreatePtrAdd(State.get(getOperand(0), Lane), in generatePerLane()
533 State.get(getOperand(1), Lane), Name); in generatePerLane()
998 assert(!State.Lane && "VPInstruction executing an Lane"); in execute()
1009 for (unsigned Lane = 0, NumLanes = State.VF.getFixedValue(); in execute() local
1010 Lane != NumLanes; ++Lane) { in execute()
1011 Value *GeneratedValue = generatePerLane(State, VPLane(Lane)); in execute()
1013 State.set(this, GeneratedValue, VPLane(Lane)); in execute()
1334 auto Lane = vputils::isSingleScalar(ExitValue) in execute() local
1343 Value *V = State.get(ExitValue, VPLane(Lane)); in execute()
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| H A D | VPlanUnroll.cpp | 461 VPLane Lane) { in cloneForLane() argument
469 if (Lane.getKind() == VPLane::Kind::ScalableLast) { in cloneForLane()
477 cast<VPInstruction>(Op)->getOperand(Lane.getKnownLane())); in cloneForLane()
481 Plan.getOrAddLiveIn(ConstantInt::get(IdxTy, Lane.getKnownLane())); in cloneForLane()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | A15SDOptimizer.cpp | 68 const DebugLoc &DL, unsigned Reg, unsigned Lane,
74 unsigned Lane, const TargetRegisterClass *TRC);
88 unsigned Lane, unsigned ToInsert);
417 unsigned Lane, bool QPR) { in createDupLane() argument
423 .addImm(Lane) in createDupLane()
432 const DebugLoc &DL, unsigned DReg, unsigned Lane, in createExtractSubreg() argument
439 .addReg(DReg, 0, Lane); in createExtractSubreg()
477 const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) { in createInsertSubreg() argument
485 .addImm(Lane); in createInsertSubreg()
542 unsigned Lane; in optimizeAllLanesPattern() local
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| /freebsd/sys/contrib/device-tree/src/arm/marvell/ |
| H A D | armada-xp-db.dts | 192 /* Port 0, Lane 0 */
196 /* Port 0, Lane 1 */
200 /* Port 0, Lane 2 */
204 /* Port 0, Lane 3 */
208 /* Port 2, Lane 0 */
212 /* Port 3, Lane 0 */
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| H A D | armada-xp-axpwifiap.dts | 100 /* Port 0, Lane 0 */
106 /* Port 0, Lane 1 */
112 /* Port 0, Lane 3 */
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| H A D | armada-395-gp.dts | 86 /* Port 1, Lane 0 */
92 /* Port 3, Lane 0 */
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| H A D | armada-385-db-ap.dts | 156 /* Port 0, Lane 0 */
161 /* Port 1, Lane 0 */
166 /* Port 2, Lane 0 */
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| H A D | armada-xp-gp.dts | 189 /* Port 0, Lane 0 */
193 /* Port 2, Lane 0 */
197 /* Port 3, Lane 0 */
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| H A D | armada-370-mirabox.dts | 120 /* Port 0, Lane 0 */
126 /* Port 1, Lane 0 */
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| H A D | armada-375-db.dts | 46 /* Port 0, Lane 0 */
51 /* Port 1, Lane 0 */
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| H A D | armada-xp-linksys-mamba.dts | 218 /* Port 0, Lane 0 */
224 /* Port 0, Lane 1 */
230 /* Port 0, Lane 3 */
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| H A D | armada-xp-netgear-rn2120.dts | 199 /* Port 0, Lane 0 */
205 /* Port 0, Lane 1 */
211 /* Port 1, Lane 0 */
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64PerfectShuffle.h | 6731 unsigned Lane = unsigned(Mask[0]); in isDUPQMask() local
6738 if (Lane >= SegmentSize) in isDUPQMask()
6746 unsigned(P.value()) == Lane + SegmentIndex * SegmentSize; in isDUPQMask()
6748 return Lane; in isDUPQMask()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/ |
| H A D | InstrMaps.h | 86 unsigned Lane = 0; in registerVector() local
91 OrigToLaneMap[Orig] = Lane; in registerVector()
92 Lane += VecUtils::getNumLanes(Orig); in registerVector()
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| /freebsd/sys/contrib/device-tree/src/arm64/marvell/ |
| H A D | armada-8040-mcbin.dtsi | 245 /* CPM Lane 5 - U29 */
292 /* CPS Lane 0 - J5 (Gigabit RJ45) */
302 /* CPS Lane 5 */
345 /* CPS Lane 1 - U32 */
351 /* CPS Lane 3 - U31 */
382 /* CPS Lane 2 - CON7 */
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| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | phy-mvebu-comphy.txt | 20 * Lane 1 (PCIe/GbE)
21 * Lane 0 (USB3/GbE)
22 * Lane 2 (SATA/USB3)
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerLowering.cpp | 243 bool matchDupFromInsertVectorElt(int Lane, MachineInstr &MI, in matchDupFromInsertVectorElt() argument
246 if (Lane != 0) in matchDupFromInsertVectorElt()
283 bool matchDupFromBuildVector(int Lane, MachineInstr &MI, in matchDupFromBuildVector() argument
286 assert(Lane >= 0 && "Expected positive lane?"); in matchDupFromBuildVector()
292 MI.getOperand(Lane < NumElements ? 1 : 2).getReg(), MRI); in matchDupFromBuildVector()
294 if (NumElements <= Lane) in matchDupFromBuildVector()
295 Lane -= NumElements; in matchDupFromBuildVector()
299 Register Reg = BuildVecMI->getOperand(Lane + 1).getReg(); in matchDupFromBuildVector()
311 int Lane = *MaybeLane; in matchDup() local
313 if (Lane < 0) in matchDup()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | LaneBitmask.h | 83 static constexpr LaneBitmask getLane(unsigned Lane) { in getLane()
84 return LaneBitmask(Type(1) << Lane); in getLane()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InterleavedAccess.cpp | 438 for (int Lane = 0; Lane < LaneCount; Lane++) in createShuffleStride() local
440 Mask.push_back((i * Stride) % LaneSize + LaneSize * Lane); in createShuffleStride()
610 int Lane = (VectorWidth / 128 > 0) ? VectorWidth / 128 : 1; in group2Shuffle() local
612 IndexGroup[(Index * 3) % (VF / Lane)] = Index; in group2Shuffle()
616 for (int i = 0; i < VF / Lane; i++) { in group2Shuffle()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 2483 auto GetSwizzleSrcs = [](size_t I, const SDValue &Lane) { in LowerBUILD_VECTOR() argument
2485 if (Lane->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
2487 const SDValue &SwizzleSrc = Lane->getOperand(0); in LowerBUILD_VECTOR()
2488 const SDValue &IndexExt = Lane->getOperand(1); in LowerBUILD_VECTOR()
2507 auto GetShuffleSrc = [&](const SDValue &Lane) { in LowerBUILD_VECTOR() argument
2508 if (Lane->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
2510 if (!isa<ConstantSDNode>(Lane->getOperand(1).getNode())) in LowerBUILD_VECTOR()
2512 if (Lane->getOperand(0).getValueType().getVectorNumElements() > in LowerBUILD_VECTOR()
2515 return Lane->getOperand(0); in LowerBUILD_VECTOR()
2547 const SDValue &Lane = Op->getOperand(I); in LowerBUILD_VECTOR() local
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/ |
| H A D | BottomUpVec.cpp | 412 unsigned Lane = 0; in emitVectors() local
429 ConstantInt *LaneC = ConstantInt::get(Type::getInt32Ty(Ctx), Lane); in emitVectors()
444 unsigned InsLane = Lane + LnCnt; in emitVectors()
450 Lane += NumLanesToInsert; in emitVectors()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 66 int Lane = -1; member
69 SpilledReg(Register R, int L) : VGPR(R), Lane(L) {} in SpilledReg()
71 bool hasLane() { return Lane != -1; } in hasLane()
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