| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | A15SDOptimizer.cpp | 68 const DebugLoc &DL, unsigned Reg, unsigned Lane,
74 unsigned Lane, const TargetRegisterClass *TRC);
88 unsigned Lane, unsigned ToInsert);
416 unsigned Lane, bool QPR) { in createDupLane() argument
422 .addImm(Lane) in createDupLane()
431 const DebugLoc &DL, unsigned DReg, unsigned Lane, in createExtractSubreg() argument
438 .addReg(DReg, 0, Lane); in createExtractSubreg()
476 const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) { in createInsertSubreg() argument
484 .addImm(Lane); in createInsertSubreg()
541 unsigned Lane; in optimizeAllLanesPattern() local
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| /freebsd/sys/contrib/device-tree/src/arm/marvell/ |
| H A D | armada-xp-db.dts | 192 /* Port 0, Lane 0 */
196 /* Port 0, Lane 1 */
200 /* Port 0, Lane 2 */
204 /* Port 0, Lane 3 */
208 /* Port 2, Lane 0 */
212 /* Port 3, Lane 0 */
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| H A D | armada-xp-axpwifiap.dts | 100 /* Port 0, Lane 0 */
106 /* Port 0, Lane 1 */
112 /* Port 0, Lane 3 */
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| H A D | armada-395-gp.dts | 86 /* Port 1, Lane 0 */
92 /* Port 3, Lane 0 */
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| H A D | armada-385-db-ap.dts | 156 /* Port 0, Lane 0 */
161 /* Port 1, Lane 0 */
166 /* Port 2, Lane 0 */
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| H A D | armada-xp-gp.dts | 189 /* Port 0, Lane 0 */
193 /* Port 2, Lane 0 */
197 /* Port 3, Lane 0 */
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| H A D | armada-375-db.dts | 46 /* Port 0, Lane 0 */
51 /* Port 1, Lane 0 */
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| H A D | armada-370-mirabox.dts | 120 /* Port 0, Lane 0 */
126 /* Port 1, Lane 0 */
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| H A D | armada-xp-linksys-mamba.dts | 218 /* Port 0, Lane 0 */
224 /* Port 0, Lane 1 */
230 /* Port 0, Lane 3 */
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| H A D | armada-xp-netgear-rn2120.dts | 199 /* Port 0, Lane 0 */
205 /* Port 0, Lane 1 */
211 /* Port 1, Lane 0 */
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| H A D | armada-388-db.dts | 133 /* Port 0, Lane 0 */
137 /* Port 1, Lane 0 */
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| H A D | armada-388-gp.dts | 219 /* Port 0, Lane 0 */
228 /* Port 1, Lane 0 */
232 /* Port 2, Lane 0 */
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| H A D | armada-370-rd.dts | 123 /* Port 0, Lane 0 */
129 /* Port 1, Lane 0 */
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VPlanSLP.cpp | 313 for (unsigned Lane = 1, E = MultiNodeOps[0].second.size(); Lane < E; ++Lane) { in reorderMultiNodeOps() local
314 LLVM_DEBUG(dbgs() << " Finding best value for lane " << Lane << "\n"); in reorderMultiNodeOps()
319 dbgs() << *cast<VPInstruction>(Ops.second[Lane])->getUnderlyingInstr() in reorderMultiNodeOps()
321 Candidates.insert(Ops.second[Lane]); in reorderMultiNodeOps()
330 VPValue *Last = FinalOrder[Op].second[Lane - 1]; in reorderMultiNodeOps()
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| H A D | VPlan.cpp | 76 Builder.getInt32(VF.getKnownMinValue() - Lane)); in getAsRuntimeExpr()
78 return Builder.getInt32(Lane); in getAsRuntimeExpr()
233 .PerPartScalars[Def][Instance.Part][Instance.Lane.mapToCacheIndex(VF)]; in get()
235 if (!Instance.Lane.isFirstLane() && in get()
244 assert(Instance.Lane.isFirstLane() && "cannot get lane > 0 for scalar"); in get()
248 Value *Lane = Instance.Lane.getAsRuntimeExpr(Builder, VF); in get() local
249 auto *Extract = Builder.CreateExtractElement(VecPart, Lane); in get()
348 for (unsigned Lane = 0; Lane < VF.getKnownMinValue(); ++Lane) in get() local
349 packScalarIntoVectorValue(Def, {Part, Lane}); in get()
406 VectorValue, ScalarInst, Instance.Lane.getAsRuntimeExpr(Builder, VF)); in packScalarIntoVectorValue()
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| H A D | VPlan.h | 172 unsigned Lane;
178 VPLane(unsigned Lane, Kind LaneKind) : Lane(Lane), LaneKind(LaneKind) {} in VPLane() argument
204 return Lane; in getKnownLane()
215 bool isFirstLane() const { return Lane == 0 && LaneKind == Kind::First; } in isFirstLane()
221 assert(VF.isScalable() && Lane < VF.getKnownMinValue()); in mapToCacheIndex()
222 return VF.getKnownMinValue() + Lane; in mapToCacheIndex()
224 assert(Lane < VF.getKnownMinValue()); in mapToCacheIndex()
225 return Lane; in mapToCacheIndex()
242 VPLane Lane; member
244 VPIteration(unsigned Part, unsigned Lane,
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| H A D | VPlanRecipes.cpp | 197 auto Lane = vputils::isUniformAfterVectorization(ExitValue) in fixPhi() local
213 Value *V = State.get(ExitValue, VPIteration(State.UF - 1, Lane)); in fixPhi()
373 const VPIteration &Lane) { in generatePerLane() argument
378 return Builder.CreatePtrAdd(State.get(getOperand(0), Lane), in generatePerLane()
379 State.get(getOperand(1), Lane), Name); in generatePerLane()
718 for (unsigned Lane = 0, NumLanes = State.VF.getKnownMinValue(); in execute() local
719 Lane != NumLanes; ++Lane) { in execute()
720 Value *GeneratedValue = generatePerLane(State, VPIteration(Part, Lane)); in execute()
722 State.set(this, GeneratedValue, VPIteration(Part, Lane)); in execute()
1451 StartLane = State.Instance->Lane.getKnownLane(); in execute()
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| /freebsd/sys/contrib/device-tree/src/arm64/marvell/ |
| H A D | armada-8040-mcbin.dtsi | 245 /* CPM Lane 5 - U29 */
292 /* CPS Lane 0 - J5 (Gigabit RJ45) */
302 /* CPS Lane 5 */
345 /* CPS Lane 1 - U32 */
351 /* CPS Lane 3 - U31 */
382 /* CPS Lane 2 - CON7 */
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| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | phy-mvebu-comphy.txt | 20 * Lane 1 (PCIe/GbE)
21 * Lane 0 (USB3/GbE)
22 * Lane 2 (SATA/USB3)
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 2081 auto GetSwizzleSrcs = [](size_t I, const SDValue &Lane) { in LowerBUILD_VECTOR() argument
2083 if (Lane->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
2085 const SDValue &SwizzleSrc = Lane->getOperand(0); in LowerBUILD_VECTOR()
2086 const SDValue &IndexExt = Lane->getOperand(1); in LowerBUILD_VECTOR()
2105 auto GetShuffleSrc = [&](const SDValue &Lane) { in LowerBUILD_VECTOR() argument
2106 if (Lane->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
2108 if (!isa<ConstantSDNode>(Lane->getOperand(1).getNode())) in LowerBUILD_VECTOR()
2110 if (Lane->getOperand(0).getValueType().getVectorNumElements() > in LowerBUILD_VECTOR()
2113 return Lane->getOperand(0); in LowerBUILD_VECTOR()
2146 const SDValue &Lane = Op->getOperand(I); in LowerBUILD_VECTOR() local
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | LaneBitmask.h | 83 static constexpr LaneBitmask getLane(unsigned Lane) { in getLane()
84 return LaneBitmask(Type(1) << Lane); in getLane()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InterleavedAccess.cpp | 441 for (int Lane = 0; Lane < LaneCount; Lane++) in createShuffleStride() local
443 Mask.push_back((i * Stride) % LaneSize + LaneSize * Lane); in createShuffleStride()
613 int Lane = (VectorWidth / 128 > 0) ? VectorWidth / 128 : 1; in group2Shuffle() local
615 IndexGroup[(Index * 3) % (VF / Lane)] = Index; in group2Shuffle()
619 for (int i = 0; i < VF / Lane; i++) { in group2Shuffle()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerLowering.cpp | 247 bool matchDupFromInsertVectorElt(int Lane, MachineInstr &MI, in matchDupFromInsertVectorElt() argument
250 if (Lane != 0) in matchDupFromInsertVectorElt()
287 bool matchDupFromBuildVector(int Lane, MachineInstr &MI, in matchDupFromBuildVector() argument
290 assert(Lane >= 0 && "Expected positive lane?"); in matchDupFromBuildVector()
297 Register Reg = BuildVecMI->getOperand(Lane + 1).getReg(); in matchDupFromBuildVector()
309 int Lane = *MaybeLane; in matchDup() local
311 if (Lane < 0) in matchDup()
312 Lane = 0; in matchDup()
313 if (matchDupFromInsertVectorElt(Lane, MI, MRI, MatchInfo)) in matchDup()
315 if (matchDupFromBuildVector(Lane, MI, MRI, MatchInfo)) in matchDup()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 58 int Lane = -1;
61 SpilledReg(Register R, int L) : VGPR(R), Lane(L) {} in hasLane()
63 bool hasLane() { return Lane != -1; }
56 int Lane = -1; global() member
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| /freebsd/sys/contrib/device-tree/src/arm64/qcom/ |
| H A D | sc7180-trogdor-lazor-r0.dts | 21 * Lane 0 was incorrectly mapped on the cable, but we've now decided
|